| 2006 | VLSID | An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | ASPDAC | A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | ASPDAC | A function generator-based reconfigurable system. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | ASPDAC | Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan |
| 2005 | FPGA | Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan |
| 2005 | VLSID | Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan |