| 2024 | DSD | SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs. | Christie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy |
| 2021 | DATE | Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis. | Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat |
| 2020 | DATE | TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. | Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi |
| 2020 | ICASSP | Energy Efficient Acceleration Of Floating Point Applications Onto CGRA. | Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy |
| 2020 | ISCAS | Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. | Ghita Harcha, Vianney Laptre, Cyrille Chavet, Philippe Coussy |
| 2019 | DATE | Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment. | Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat |
| 2019 | DATE | Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs. | Satyajit Das, Kevin J. M. Martin, Philippe Coussy |
| 2019 | ICASSP | Solving Memory Access Conflicts in LTE-4G Standard. | Cyrille Chavet, Fabrice Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy |
| 2018 | ISCAS | A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. | Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi |
| 2017 | ASPDAC | Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. | Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini |
| 2017 | ISCAS | A 142MOPS/mW integrated programmable array accelerator for smart visual processing. | Satyajit Das, Davide Rossi, Kevin J. M. Martin, Philippe Coussy, Luca Benini |
| 2016 | DATE | A dynamically reconfigurable ECC decoder architecture. | Awais Sani, Philippe Coussy, Cyrille Chavet |
| 2015 | DATE | In-place memory mapping approach for optimized parallel hardware interleaver architectures. | Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani |
| 2015 | ISCAS | Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. | Robin Danilo, Hooman Jarollahi, Vincent Gripon, Philippe Coussy, Laura Conde-Canencia, Warren J. Gross |
| 2015 | ISCAS | Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. | Hugues Wouafo, Cyrille Chavet, Philippe Coussy |
| 2014 | DATE | A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters. | Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini |
| 2014 | EUC | A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory. | Paolo Burgio, Andrea Marongiu, Philippe Coussy, Luca Benini |
| 2014 | ICASSP | Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. | Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy |
| 2014 | ISCAS | A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators. | Mohamed Ben Hammouda, Philippe Coussy, Loc Lagadec |
| 2013 | FPL | Dynamic branch prediction for high-level synthesis. | Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo |
| 2013 | ICASSP | On-chip implementation of memory mapping algorithm to support flexible decoder architecture. | Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet |
| 2012 | DSD | OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. | Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini |
| 2011 | ICASSP | A methodology based on Transportation problem modeling for designing parallel interleaver architectures. | Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin |
| 2011 | ISCAS | An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. | Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin |
| 2010 | FPL | Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. | Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin |
| 2010 | ICASSP | Static Address Generation Easing: a design methodology for parallel interleaver architectures. | Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin |
| 2010 | ISCAS | A memory mapping approach for parallel interleaver design with multiples read and write accesses. | Cyrille Chavet, Philippe Coussy |
| 2007 | ICCAD | A design flow dedicated to multi-mode architectures for DSP applications. | Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin |
| 2007 | ISCAS | A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. | Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin |
| 2005 | FDL | SystemCmantic: A high level Modelling and Co-Design Framework. | Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart |
| 2005 | ICASSP | A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. | Philippe Coussy, Gwenol Corre, Pierre Bomel, Eric Senn, Eric Martin |
| 2005 | ISCAS | High-level synthesis under I/O timing and memory constraints. | Philippe Coussy, Gwenol Corre, Eric Senn, Pierre Bomel, Eric Martin |
| 2004 | ICASSP | A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. | Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin |
| 2002 | ISCAS | A design methodology for IP integration. | Philippe Coussy, Adel Baganne, Eric Martin |