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Piet Engelke

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

22

Venues

8

Active years

2000–2020

Best venue rank

A*

Where they publish

Papers

22 indexed papers, newest first.

YearVenueTitleAuthors
2020ITCIJTAG Through a Two-Pin Chip Interface.Manu Baby, Bernd Bttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, Jean-Franois Ct, Givargis Danialy, Martin Keim, Lori Schramm
2017DATEBASTION: Board and SoC test instrumentation for ageing and no failure found.Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke
2014DACAdvanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.Felix Reimann, Michael Gla, Jrgen Teich, Alejandro Cook, Laura Rodrguez Gmez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein
2014DATENon-intrusive integration of advanced diagnosis features in automotive E/E-architectures.Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Gla, Felix Reimann, Laura Rodrguez Gmez, Thomas Russ, Jrgen Teich, Dominik Ull, Hans-Joachim Wunderlich
2013DDECSOn the feasibility of combining on-line-test and self repair for logic circuits.Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus
2012DSDScan Based Tests via Standard Interfaces.Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke
2012ETSFunding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehicles.Piet Engelke, Hermann Obermeir
2009VLSIDTIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
2009VTSAn Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker
2008DATEResistive Bridging Fault Simulation of Industrial Circuits.Piet Engelke, Ilia Polian, Jrgen Schlffel, Bernd Becker
2008DDECSDiagnosis of Realistic Defects Based on the X-Fault Model.Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
2008ETSA Simulator of Small-Delay Faults Caused by Resistive-Open Defects.Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
2008ITCExtraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2008VTSAutomatic Test Pattern Generation for Interconnect Open Defects.Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2005ETSA unified fault model and test generation procedure for interconnect opens and bridges.Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
2005VTSResistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.Ilia Polian, Sandip Kundu, Jean-Marc Gallire, Piet Engelke, Michel Renovell, Bernd Becker
2004ETSAutomatic test pattern generation for resistive bridging faults.Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2004ITCX-Masking During Logic BIST and Its Impact on Defect Coverage.Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
2004VTSThe Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
2003ETSModeling feedback bridging faults with non-zero resistance.Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
2003ITCSimulating Resistive Bridging and Stuck-At Faults.Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2000ETSA parameterizable fault simulator for bridging faults.Piet Engelke, Bernd Becker, Martin Keim