| 2026 | VLSID | Design and FPGA Implementation of Power and Area Efficient Multi-Stage Accelerator for Depthwise Separable Convolutions. | Srishti Misra, Rahul Shrestha |
| 2026 | VLSID | A Novel VLSI Architecture and FPGA Implementation of Hardware-Efficient Mfocuss-Based Wideband Spectrum Sensor for Dynamic Spectrum Access. | Aayush Shrivas, Rahul Shrestha |
| 2025 | VLSID | CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber. | Alip Majumdar, Rahul Shrestha |
| 2024 | VLSID | Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator. | Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury |
| 2023 | VLSID | Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. | Meghvern Pathak, Rahul Shrestha |
| 2021 | ISCAS | Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network. | Rohit B. Chaurasiya, Rahul Shrestha |
| 2020 | ISCAS | A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network. | Rahul Shrestha, Shubham Sanjay Telgote |
| 2020 | ISCAS | A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard. | Anuj Verma, Rahul Shrestha |
| 2020 | VLSID | A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. | Anuj Verma, Rahul Shrestha |
| 2019 | ISCAS | Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED Based Spectrum Sensor for Cognitive Radio. | Rohit B. Chaurasiya, Rahul Shrestha |
| 2019 | VLSID | High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio. | Rahul Shrestha, Pooja Bansal, Srikant Srinivasan |
| 2018 | ICCD | Parameterized Posit Arithmetic Hardware Generator. | Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers |
| 2018 | VLSID | Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network. | Mahesh S. Murty, Rahul Shrestha |
| 2016 | VLSID | Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier. | Rahul Shrestha, Utkarsh Rastogiy |
| 2013 | VLSID | Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding. | Rahul Shrestha, Roy P. Paily |