| 2008 | ITC | Achieving Zero-Defects for Automotive Applications. | Rajesh Raina |
| 2006 | ITC | What is DFM & DFY and Why Should I Care ? | Rajesh Raina |
| 2005 | ITC | Is the concern for soft-error overblown? | Rajesh Raina |
| 2005 | ITC | Is the concern for soft-error overblown? | Rajesh Raina |
| 2005 | ITC | Have we overcome the challenges associated with SoC and multi-core testing? | Rajesh Raina |
| 2005 | ITC | Have we overcome the challenges associated with SoC and multi-core testing? | Rajesh Raina |
| 2002 | ITC | Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. | Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina |
| 2002 | ITC | Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . | Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead |
| 2002 | ITC | valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits. | John Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns |
| 2002 | ITC | A Wavelet-Based Timing Parameter Extraction Method. | Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina |
| 2002 | VTS | Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
| 2001 | ITC | Testing clock distribution circuits using an analytic signal method. | Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida |
| 2001 | VTS | A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen |
| 2000 | ITC | DFT advances in Motorola's Next-Generation 74xx PowerPC | Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan |
| 2000 | ITC | Jitter measurements of a PowerPC | Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe |
| 2000 | VTS | At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. | Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina |
| 1999 | ITC | Design-for-test methodology for Motorola PowerPC microprocessors. | Magdy S. Abadir, Rajesh Raina |
| 1999 | ITC | DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. | Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar |
| 1997 | DAC | Efficient Testing of Clock Regenerator Circuits in Scan Designs. | Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh |
| 1997 | ITC | How Seriously Do You Take Your Possible-Detect Faults? | Rajesh Raina, Charles Njinda, Robert F. Molyneaux |
| 1997 | VLSID | T4: Verification. | Rajesh Raina, Jacob A. Abraham, A. K. Pujari |
| 1996 | DAC | Functional Verification Methodology for the PowerPC 604 Microprocessor. | James Monaco, David Holloway, Rajesh Raina |