| 2026 | DDECS | Pulsed Electromagnetic Fault Injection on Ro-Based True Random Number Generators in FPGAs. | Sami El Amraoui, Mahdi Allaw, Florian Pebay-Peyroula, Rgis Leveugle, Paolo Maistri |
| 2025 | DSD | Pulsed ElectroMagnetic Fault Injection Attack on a Time Measurement-based Arbiter-PUF. | Azzadine Thajte, Sami El Amraoui, Paolo Maistri, Rgis Leveugle, Giorgio Di Natale, Laurent Fesquet |
| 2025 | ETS | Pulsed Electromagnetic Fault Injection Attack on Ring Oscillator-based PUFs in FPGAs. | Sami El Amraoui, Aghiles Douadi, Rgis Leveugle, Paolo Maistri |
| 2024 | DDECS | Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. | Sami El Amraoui, Rgis Leveugle, Paolo Maistri |
| 2022 | IOLTS | Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. | Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Rgis Leveugle |
| 2021 | ITC | Security EDA Extension through P1687.1 and 1687 Callbacks. | Michele Portolan, Vincent Reynaud, Paolo Maistri, Rgis Leveugle, Giorgio Di Natale |
| 2020 | DDECS | Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. | Julie Roux, Vincent Beroulle, Katell Morin-Allory, Rgis Leveugle, Lilian Bossuet, Frdric Czilly, Frdric Berthoz, Gilles Genvrier, Franois Cerisier |
| 2020 | ETS | Dynamic Authentication-Based Secure Access to Test Infrastructure. | Michele Portolan, Vincent Reynaud, Paolo Maistri, Rgis Leveugle |
| 2020 | IOLTS | A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. | Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragn, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Rgis Leveugle, Salvador Mir |
| 2019 | ETS | Alternatives to Fault Injections for Early Safety/Security Evaluations. | Michele Portolan, Alessandro Savino, Rgis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale |
| 2019 | ETS | Approximate computing design exploration through data lifetime metrics. | Alessandro Savino, Michele Portolan, Rgis Leveugle, Stefano Di Carlo |
| 2018 | FDTC | Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. | Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hly, Rgis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre |
| 2018 | IOLTS | The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. | Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hly, Rgis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre |
| 2017 | DDECS | HLS design of a hardware accelerator for Homomorphic Encryption. | Asma Mkhinini, Paolo Maistri, Rgis Leveugle, Rached Tourki |
| 2017 | IOLTS | Reliability of computing systems: From flip flops to variables. | Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Rgis Leveugle |
| 2016 | DATE | On the development of a new countermeasure based on a laser attack RTL fault model. | Charalampos Ananiadis, Athanasios Papadimitriou, David Hly, Vincent Beroulle, Paolo Maistri, Rgis Leveugle |
| 2016 | DSD | HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. | Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Rgis Leveugle, Frdric Rousseau |
| 2016 | IOLTS | Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. | K. Chibani, Michele Portolan, Rgis Leveugle |
| 2014 | DATE | A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. | Athanasios Papadimitriou, David Hly, Vincent Beroulle, Paolo Maistri, Rgis Leveugle |
| 2014 | DSD | An Elliptic Curve Crypto-Processor Secured by Randomized Windows. | Simon Pontie, Paolo Maistri, Rgis Leveugle |
| 2013 | IOLTS | Evaluating a low cost robustness improvement in SRAM-based FPGAs. | Mohamed Ben Jrad, Rgis Leveugle |
| 2011 | DSD | 10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. | Paolo Maistri, Rgis Leveugle |
| 2011 | ITP | Towards Robustness Analysis Using PVS. | Renaud Clavel, Laurence Pierre, Rgis Leveugle |
| 2010 | ETS | Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. | Gaetan Canivet, P. Maistn, Rgis Leveugle, Frdric Valette, Jessy Cldire, Marc Renaudin |
| 2010 | FDL | Early Robustness Evaluation of Digital Integrated Systems. | Rgis Leveugle |
| 2009 | DATE | Statistical fault injection: Quantified error and confidence. | Rgis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert |
| 2009 | IOLTS | Towards automated fault pruning with Petri Nets. | Paolo Maistri, Rgis Leveugle |
| 2009 | VTS | Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. | Gaetan Canivet, Rgis Leveugle, Jessy Cldire, Frdric Valette, Marc Renaudin |
| 2008 | IOLTS | Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. | Gaetan Canivet, Jessy Cldire, Jean Baptiste Ferron, Frdric Valette, Marc Renaudin, Rgis Leveugle |
| 2008 | IOLTS | Software Self-Testing of a Symmetric Cipher with Error Detection Capability. | Paolo Maistri, Cyril Excoffon, Rgis Leveugle |
| 2007 | DATE | Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. | Rgis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria |
| 2007 | FDTC | A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. | Paolo Maistri, Pierre Vanhauwaert, Rgis Leveugle |
| 2007 | IOLTS | Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2006 | DDECS | On the Use of Information Redundancy When Designing Secure Chips. | Rgis Leveugle, V. Maingot |
| 2006 | DDECS | A Flexible SoPC-based Fault Injection Environment. | Pierre Vanhauwaert, Rgis Leveugle, Philippe Roche |
| 2006 | FDTC | Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. | Yannick Monnet, Marc Renaudin, Rgis Leveugle, Christophe Clavier, Pascal Moitrel |
| 2006 | IOLTS | Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. | Yannick Monnet, Marc Renaudin, Rgis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet |
| 2005 | DAC | Asynchronous circuits transient faults sensitivity evaluation. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2005 | EUC | Towards a Secure and Reliable System. | Michele Portolan, Rgis Leveugle |
| 2005 | IOLTS | Evaluation of SET and SEU Effects at Multiple Abstraction Levels. | Lorena Anghel, Rgis Leveugle, Pierre Vanhauwaert |
| 2005 | IOLTS | Introduction to the Special Session on Secure Implementations. | Rgis Leveugle |
| 2005 | IOLTS | A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. | Rgis Leveugle |
| 2005 | IOLTS | On-Line Testing for Secure Implementations: Design and Validation. | Rgis Leveugle, Yervant Zorian, Luca Breveglieri, Andr K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert |
| 2005 | IOLTS | Hardening Techniques against Transient Faults for Asynchronous Circuits. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2005 | IOLTS | On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. | Michele Portolan, Rgis Leveugle |
| 2004 | DATE | Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. | Rgis Leveugle, Abdelaziz Ammari |
| 2004 | IOLTS | On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. | Abdelaziz Ammari, K. Hadjiat, Rgis Leveugle |
| 2004 | IOLTS | Asynchronous Circuits Sensitivity to Fault Injection. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2004 | IOLTS | Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. | Michele Portolan, Rgis Leveugle |
| 2002 | DATE | Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. | Rgis Leveugle |
| 2002 | IOLTS | Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. | Rgis Leveugle, K. Hadjiat |
| 1996 | VTS | Standard and ROM-based synthesis of FSMs with control flow checking capabilities. | X. Wendling, Raphal Rochet, Rgis Leveugle |
| 1995 | DATE | Efficient synthesis of fault-tolerant controllers. | Raphal Rochet, Rgis Leveugle, Gabriele Saucier |
| 1993 | DAC | Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. | Rgis Leveugle |
| 1993 | ICCD | Influence of Error Correlations on the Signature Analysis Aliasing. | Rgis Leveugle, X. Delord, Gabriele Saucier |
| 1991 | ITC | Hierarchical Test Generation Based on Delayed Propagation. | Margot Karam, Rgis Leveugle, Gabriele Saucier |
| 1989 | ICCD | Concurrent checking in dedicated controllers. | Rgis Leveugle, Gabriele Saucier |
| 1989 | ICCD | A channelless layout for multilevel synthesis with compiled cells. | Gabriele Saucier, Rgis Leveugle, Pierre Abouzeid |
| 1989 | ITC | Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. | Rgis Leveugle, Gabriele Saucier |