| 2026 | IOLTS | Progressive Error-Aware ECC Techniques for Enhancing Flash Memory Reliability. | Shyue-Kung Lu, Jie-Xin Shi, Shi-Yu Huang, Kohei Miyase |
| 2024 | ETS | Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. | Cheng-Wen Wu, Shi-Yu Huang |
| 2024 | ITC | Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test. | Chi Lai, Shi-Yu Huang |
| 2023 | FPL | Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. | Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer |
| 2022 | ITC | Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning. | Chen-Lin Tsai, Shi-Yu Huang |
| 2020 | ICCD | Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz. | Wei Chu, Wei-Hao Chen, Shi-Yu Huang |
| 2020 | ITC | Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. | Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang |
| 2019 | ASPDAC | Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. | Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng |
| 2019 | DAC | The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop. | Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang |
| 2019 | ITC | Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration. | Wei Chu, Shi-Yu Huang |
| 2019 | ITC | International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. | Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian |
| 2017 | ICCD | DLL-Assisted Clock Synchronization Method for Multi-Die ICs. | Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou |
| 2016 | ETS | Testing of small delay faults in a clock network. | Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng |
| 2016 | ITC | Online slack-time binning for IO-registered die-to-die interconnects. | Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng |
| 2015 | DATE | Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. | Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng |
| 2015 | ITC | Monitoring the delay of long interconnects via distributed TDC. | Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng |
| 2014 | ETS | On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. | Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng |
| 2013 | IOLTS | At-speed BIST for interposer wires supporting on-the-spot diagnosis. | Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng |
| 2013 | ITC | Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. | Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng |
| 2012 | DAC | Small delay testing for TSVs in 3-D ICs. | Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai |
| 2012 | ITC | A unified method for parametric fault characterization of post-bond TSVs. | Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter |
| 2011 | DAC | PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. | Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh |
| 2011 | DAC | A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. | Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang |
| 2011 | DATE | Black-box leakage power modeling for cell library and SRAM compiler. | Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen |
| 2011 | ITC | A fully cell-based design for timing measurement of memory. | Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao |
| 2010 | ASPDAC | PAC duo system power estimation at ESL. | Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang |
| 2009 | DATE | QC-Fill: An X-Fill method for quick-and-cool scan test. | Chao-Wen Tzeng, Shi-Yu Huang |
| 2006 | DAC | A network security processor design based on an integrated SOC design and test platform. | Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang |
| 2005 | ASPDAC | Power estimation starategies for a low-power security processor. | Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang |
| 2005 | ICCD | Quick Scan Chain Diagnosis Using Signal Profiling. | Jheng-Syun Yang, Shi-Yu Huang |
| 2003 | DATE | Decomposition of Extended Finite State Machine for Low Power Design. | MingHung Lee, TingTing Hwang, Shi-Yu Huang |
| 2003 | ISCAS | Combinational circuit fault diagnosis using logic emulation. | Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang |
| 2002 | VTS | Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. | Shi-Yu Huang |
| 2001 | ASPDAC | Towards the logic defect diagnosis for partial-scan designs. | Shi-Yu Huang |
| 2001 | ASPDAC | On speeding up extended finite state machines using catalyst circuitry. | Shi-Yu Huang |
| 2001 | VTS | On Improving the Accuracy Of Multiple Defect Diagnosis. | Shi-Yu Huang |
| 1998 | ASPDAC | A Hybrid Power Model for RTL Power Estimation. | Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho |
| 1998 | DAC | Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu |
| 1997 | ASPDAC | AQUILA: An equivalence verifier for large sequential circuits. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen |
| 1997 | ITC | Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng |
| 1997 | VTS | Incremental logic rectification. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
| 1996 | DAC | Error Correction Based on Verification Techniques. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
| 1996 | DAC | Compact Vector Generation for Accurate Power Simulation. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee |
| 1996 | ISLPED | A novel methodology for transistor-level power estimation. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee |
| 1996 | ITC | An ATPG-Based Framework for Verifying Sequential Equivalence. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Glser |
| 1995 | ICCAD | Fault emulation: a new approach to fault grading. | Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai |