Shunsuke Okumura
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
2009–2013
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ASPDAC | A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. | Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2013 | ASPDAC | A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. | Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2012 | ISLPED | A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. | Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2011 | DSN | Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. | Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2010 | ISLPED | 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. | Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2009 | VLSID | A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto |