| 2012 | DATE | Test generation for clock-domain crossing faults in integrated circuits. | Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil |
| 2009 | VTS | RT-Level Deviation-Based Grading of Functional Test Sequences. | Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti |
| 2008 | DATE | A low-cost concurrent error detection technique for processor control logic. | Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche |
| 2006 | ITC | A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. | Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz |
| 2006 | VTS | Path Delay Fault Simulation on Large Industrial Designs. | Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty |
| 1994 | ITC | Design of an Efficient Weighted-Random-Pattern Generation System. | Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams |
| 1994 | VTS | On broad-side delay test. | Jacob Savir, Srinivas Patil |
| 1992 | ITC | Skewed-Load Transition Test: Part 2, Coverage. | Srinivas Patil, Jacob Savir |
| 1991 | DAC | Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. | Srinivas Patil, Prithviraj Banerjee, Janak H. Patel |
| 1991 | ITC | A Layout Driven Design for Testability Technique for MOS VLSI Circuits. | Sungho Kim, Prithviraj Banerjee, Srinivas Patil |
| 1989 | DAC | A Parallel Branch and Bound Algorithm for Test Generation. | Srinivas Patil, Prithviraj Banerjee |
| 1989 | ICCD | A test generation system for path delay faults. | Srinivas Patil, Sudhakar M. Reddy |
| 1989 | ITC | Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. | Srinivas Patil, Prithviraj Banerjee |
| 1989 | SC | Efficient circuit partitioning algorithms for parallel logic simulation. | Srinivas Patil, Prithviraj Banerjee, Constantine D. Polychronopoulos |