| 2024 | EGVE | Advanced Motion Prediction for Virtual Reality Gaming: a CNN-Based Approach. | Hubert Jegierski, Maciej Jegierski, Adrian Lapczynski, Pawel Babiuch, Miroslaw Plaza, Pawel Pieta, Grzegorz Lukawski, Stanislaw Deniziak, Jacek Opalka, Artur Jasinski, Magdalena Igras-Cybulska, Pawel Wegrzyn |
| 2024 | VR | MUN: an AI-powered multiplayer networking solution for VR games. | Pawel Babiuch, Adrian Lapczynski, Hubert Jegierski, Maciej Jegierski, Rafal Salamon, Barbara Kolber-Bugajska, Mirosaw Paza, Stanislaw Deniziak, Pawel Pieta, Grzegorz Lukawski, Artur Jasinski, Jacek Opalka, Alicia Marmon, Kamil Kwiatkowski, Artur Cybulski, Magdalena Igras-Cybulska, Pawel Wegrzyn |
| 2023 | FedCSIS | Real-time Communication Model for IoT Systems. | Stanislaw Deniziak, Miroslaw Plaza, Lukasz Arcab |
| 2020 | DDECS | Scheduling of Distributed Applications in HHPCaaS Clouds for Internet of Things. | Stanislaw Deniziak, Slawomir Bak |
| 2020 | DDECS | Synthesis of Self-Adaptable Software for Multicore Embedded Systems. | Stanislaw Deniziak, Leszek Ciopinski |
| 2018 | FedCSIS | Query by Approximate Shapes Image Retrieval with improved object sketch extraction algorithm. | Stanislaw Deniziak, Tomasz Michno |
| 2018 | MICRO | Codesign of energy and resource efficient contention-free Network-on Chip for real-time embedded systems. | Stanislaw Deniziak, Robert Tomaszewski |
| 2017 | FedCSIS | New Content Based Image Retrieval database structure using Query by Approximate Shapes. | Stanislaw Deniziak, Tomasz Michno |
| 2017 | FedCSIS | Business Intelligence Platform for Big Data based on Scalable Distributed Two-Layer Data Store. | Adam Krechowicz, Stanislaw Deniziak |
| 2016 | DSD | Synthesis of Multivalued Logical Networks for FPGA Implementations. | Stanislaw Deniziak, Mariusz Wisniewski, Karol Wieczorek |
| 2016 | FedCSIS | Content Based Image Retrieval using Query by Approximate Shape. | Stanislaw Deniziak, Tomasz Michno |
| 2015 | FedCSIS | Synthesis of power aware adaptive schedulers for embedded systems using developmental genetic programming. | Stanislaw Deniziak, Leszek Ciopinski |
| 2015 | FedCSIS | The scalable distributed two-layer Content Based Image Retrieval data store. | Stanislaw Deniziak, Tomasz Michno, Adam Krechowicz |
| 2015 | HSI | Query-by-Shape interface for Content Based Image Retrieval. | Stanislaw Deniziak, Tomasz Michno |
| 2015 | PPAM | Scalable Distributed Two-Layer Block Based Datastore. | Adam Krechowicz, Stanislaw Deniziak, Mariusz Bedla, Arkadiusz Chrobot, Grzegorz Lukawski |
| 2014 | FedCSIS | Synthesis of Real Time Distributed Applications for Cloud Computing. | Slawomir Bak, Stanislaw Deniziak |
| 2014 | FedCSIS | An Application of Developmental Genetic Programming for Automatic Creation of Supervisors of Multi-task Real-Time Object-Oriented Systems. | Krzysztof Sapiecha, Leszek Ciopinski, Stanislaw Deniziak |
| 2014 | UCC | Cost Optimization of Real-Time Cloud Applications Using Developmental Genetic Programming. | Stanislaw Deniziak, Leszek Ciopinski, Grzegorz Pawinski, Karol Wieczorek, Slawomir Bak |
| 2012 | ICAISC | Evolutionary Optimization of Decomposition Strategies for Logical Functions. | Stanislaw Deniziak, Karol Wieczorek |
| 2011 | PPAM | Parallel Approach to the Functional Decomposition of Logical Functions Using Developmental Genetic Programming. | Stanislaw Deniziak, Karol Wieczorek |
| 2009 | DDECS | Contention-avoiding custom topology generation for network-on-chip. | Stanislaw Deniziak, Robert Tomaszewski |
| 2009 | DDECS | A symbolic RTL synthesis for LUT-based FPGAs. | Stanislaw Deniziak, Mariusz Wisniewski |
| 2008 | DDECS | Rapid Prototyping of NoC Architectures from a SystemC Specification. | Stanislaw Deniziak, Robert Tomaszewski |
| 2008 | DDECS | An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs. | Stanislaw Deniziak, Mariusz Wisniewski |
| 2008 | FPL | An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. | Stanislaw Deniziak, Mariusz Wisniewski |
| 2007 | DDECS | Resource Constrained Co-synthesis of Self-reconfigurable SOPCs. | Radoslaw Czarnecki, Stanislaw Deniziak |
| 2003 | DSD | An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. | Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha |
| 1994 | ISCAS | Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based Systems. | Stanislaw Deniziak, Krzysztof Sapiecha |