| 2025 | FCCM | Chronbench: An Incremental HDL Benchmark Suite. | Zakary Nafziger, Steven J. E. Wilton |
| 2025 | FPL | Open-Source FPGA Routing Runtime Prediction for Improved Productivity Via Smart Route Termination. | Andrew David Gunter, Steven J. E. Wilton |
| 2025 | FPL | Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route Termination. | Andrew David Gunter, Steven J. E. Wilton |
| 2025 | FPL | Using Data to Reduce Uncertainty in FPGA Routing. | Andrew David Gunter, Steven J. E. Wilton |
| 2025 | ICML | QUTE: Quantifying Uncertainty in TinyML models with Early-exit-assisted ensembles for model-monitoring. | Nikhil Pratap Ghanathe, Steven J. E. Wilton |
| 2024 | QCE | Structural Modifications in Quantum-Assisted Training for General Boltzmann Machines. | Jose P. Pinilla, Steven J. E. Wilton |
| 2024 | QCE | Quantum-Assisted Machine Learning Framework: Training and Evaluation of Boltzmann Machines Using Quantum Annealers. | Jose P. Pinilla, Steven J. E. Wilton |
| 2023 | FCCM | A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems. | Andrew David Gunter, Steven J. E. Wilton |
| 2023 | FCCM | Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. | Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon |
| 2023 | FPGA | Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems. | Andrew David Gunter, Steven J. E. Wilton |
| 2022 | SC | Positive-Phase Temperature Scaling for Quantum-Assisted Boltzmann Machine Training. | Jose P. Pinilla, Steven J. E. Wilton |
| 2021 | FCCM | Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. | Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton |
| 2020 | FPL | Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. | Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton |
| 2019 | FPGA | On-chip FPGA Debug Instrumentation for Machine Learning Applications. | Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton |
| 2019 | ICCAD | Towards In-Circuit Tuning of Deep Learning Designs. | Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk |
| 2018 | ETS | Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. | Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton |
| 2018 | FPGA | Architecture Exploration for HLS-Oriented FPGA Debug Overlays. | Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton |
| 2018 | FPL | An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. | Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton |
| 2017 | FPL | Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. | Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton |
| 2016 | FPL | Quantifying observability for in-system debug of high-level synthesis circuits. | Jeffrey Goeders, Steven J. E. Wilton |
| 2015 | FCCM | Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. | Jeffrey B. Goeders, Steven J. E. Wilton |
| 2014 | FPL | High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. | Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas |
| 2014 | FPL | Incremental distributed trigger insertion for efficient FPGA debug. | Fatemeh Eslami, Steven J. E. Wilton |
| 2014 | FPL | Effective FPGA debug for high-level synthesis generated circuits. | Jeffrey B. Goeders, Steven J. E. Wilton |
| 2013 | FCCM | Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. | Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton |
| 2013 | FPGA | Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. | Eddie Hung, Steven J. E. Wilton |
| 2012 | FPGA | A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. | Assem A. M. Bsoul, Steven J. E. Wilton |
| 2012 | FPL | Limitations of incremental signal-tracing for FPGA debug. | Eddie Hung, Steven J. E. Wilton |
| 2011 | FPGA | Towards scalable FPGA CAD through architecture. | Scott Y. L. Chin, Steven J. E. Wilton |
| 2011 | FPGA | An analytical model relating FPGA architecture parameters to routability. | Joydip Das, Steven J. E. Wilton |
| 2011 | FPL | Speculative Debug Insertion for FPGAs. | Eddie Hung, Steven J. E. Wilton |
| 2010 | FPGA | The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
| 2009 | FPGA | Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. | Alastair M. Smith, Steven J. E. Wilton, Joydip Das |
| 2009 | FPL | An analytical model relating FPGA architecture and place and route runtime. | Scott Y. L. Chin, Steven J. E. Wilton |
| 2009 | FPL | Improving the memory footprint and runtime scalability of FPGA CAD algorithms. | Scott Y. L. Chin, Steven J. E. Wilton |
| 2009 | FPL | Modeling post-techmapping and post-clustering FPGA circuit depth. | Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk |
| 2008 | FMCAD | BackSpace: Formal Analysis for Post-Silicon Debug. | Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang |
| 2008 | FPL | Rapid estimation of power consumption for hybrid FPGAs. | Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton |
| 2008 | FPL | An analytical model describing the relationships between logic architecture and FPGA density. | Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk |
| 2007 | FPGA | GlitchLess: an active glitch minimization technique for FPGAs. | Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton |
| 2007 | FPGA | A synthesizable datapath-oriented embedded FPGA fabric. | Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton |
| 2007 | FPL | Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. | Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton |
| 2007 | FPL | Clock-Aware Placement for FPGAs. | Julien Lamoureux, Steven J. E. Wilton |
| 2007 | FPL | Embedded Programmable Logic Core Enhancements for System Bus Interfaces. | Bradley R. Quinton, Steven J. E. Wilton |
| 2006 | FCCM | Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. | Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio Lpez-Buedo |
| 2006 | FPGA | FPGA clock network architecture: flexibility vs. area and power. | Julien Lamoureux, Steven J. E. Wilton |
| 2006 | FPL | Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. | Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton |
| 2006 | FPL | Activity Estimation for Field-Programmable Gate Arrays. | Julien Lamoureux, Steven J. E. Wilton |
| 2006 | FPL | Architecture and CAD for FPGA Clock Networks. | Julien Lamoureux, Steven J. E. Wilton |
| 2005 | FCCM | Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. | Zion S. Kwok, Steven J. E. Wilton |
| 2005 | ICCD | Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
| 2005 | ISCAS | Concentrator access networks for programmable logic cores on SoCs. | Bradley R. Quinton, Steven J. E. Wilton |
| 2005 | ISLPED | Challenges and opportunities for low power FPGAs in nanometer technologies. | Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton |
| 2004 | FPL | The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. | Steven J. E. Wilton, Su-Shin Ang, Wayne Luk |
| 2004 | ISCAS | An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. | Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux |
| 2003 | FPGA | Architectures and algorithms for synthesizable embedded programmable logic cores. | Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton |
| 2003 | ICCAD | On the Interaction Between Power-Aware FPGA CAD Algorithms. | Julien Lamoureux, Steven J. E. Wilton |
| 2002 | FPGA | On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. | Andy Yan, Rebecca Cheng, Steven J. E. Wilton |
| 2002 | FPL | A Flexible Power Model for FPGAs. | Kara K. W. Poon, Andy Yan, Steven J. E. Wilton |
| 2001 | FPGA | Detailed routing architectures for embedded programmable logic IP cores. | Peter Hallschmid, Steven J. E. Wilton |
| 2001 | FPGA | A crosstalk-aware timing-driven router for FPGAs. | Steven J. E. Wilton |
| 2001 | FPL | Macrocell Architectures for Product Term Embedded Memory Arrays. | Ernie Lin, Steven J. E. Wilton |
| 2000 | FPGA | Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. | Steven J. E. Wilton |
| 2000 | FPL | FPGA Implementation of a Prototype WDM On-Line Scheduler. | Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh |
| 1999 | FPL | Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. | William K. C. Ho, Steven J. E. Wilton |
| 1999 | FPL | A New Switch Block for Segmented FPGAs. | M. Imran Masud, Steven J. E. Wilton |
| 1998 | FPGA | SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. | Steven J. E. Wilton |
| 1997 | FPGA | Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
| 1995 | FPGA | Architecture of Centralized Field-Configurable Memory. | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
| 1994 | ISCA | Tradeoffs in Two-Level On-Chip Caching. | Norman P. Jouppi, Steven J. E. Wilton |
| 1993 | ISCAS | A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. | Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton |