| 2025 | ISLPED | ML-Power: Machine Learning based Power Estimation for SoCs. | Sujay Pandit, Sujit Dey, Anand Raghunathan |
| 2023 | CHASE | Short: Deep Learning Approach to Skeletal Performance Evaluation of Physical Therapy Exercises. | Bhanu Garg, Alexander Postlmayr, Pamela C. Cosman, Sujit Dey |
| 2022 | VTC | Adaptive C-V2X Sidelink Communications for Vehicular Applications Beyond Safety Messages. | Yu-Jen Ku, Bryse Flowers, Samuel Thornton, Sabur Baidya, Sujit Dey |
| 2021 | PIMRC | Low Overhead Codebook Design for mmWave Roadside Units Placed at Smart Intersections. | Bryse Flowers, Xinyu Zhang, Sujit Dey |
| 2020 | DAC | Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle Applications. | Sabur Baidya, Yu-Jen Ku, Hengyu Zhao, Jishen Zhao, Sujit Dey |
| 2020 | MOBICOM | X-Array: approximating omnidirectional millimeter-wave coverage using an array of phased arrays. | Song Wang, Jingqi Huang, Xinyu Zhang, Hyoil Kim, Sujit Dey |
| 2019 | GLOBECOM | Head and Body Motion Prediction to Enable Mobile VR Experiences with Low Latency. | Xueshi Hou, Jianzhong Zhang, Madhukar Budagavi, Sujit Dey |
| 2019 | HealthCom | Personalized Blood Pressure Estimation using Photoplethysmography and Wavelet Decomposition. | Jared Leitner, Po-Han Chiang, Sujit Dey |
| 2019 | VTC | Sustainable Vehicular Edge Computing Using Local and Solar-Powered Roadside Unit Resources. | Yu-Jen Ku, Sujit Dey |
| 2018 | HealthCom | Personalized Effect of Health Behavior on Blood Pressure: Machine Learning Based Prediction and Recommendation. | Po-Han Chiang, Sujit Dey |
| 2018 | ICCCN | Quality of Service Optimization for Vehicular Edge Computing with Solar-Powered Road Side Units. | Yu-Jen Ku, Po-Han Chiang, Sujit Dey |
| 2018 | SIGCOMM | Predictive View Generation to Enable Mobile 360-degree and VR Experiences. | Xueshi Hou, Sujit Dey, Jianzhong Zhang, Madhukar Budagavi |
| 2017 | ICCCN | Wireless VR/AR with Edge/Cloud Computing. | Xueshi Hou, Yao Lu, Sujit Dey |
| 2016 | ISM | A Novel Hyper-Cast Approach to Enable Cloud-Based Virtual Classroom Applications. | Xueshi Hou, Yao Lu, Sujit Dey |
| 2015 | HealthCom | Motion data alignment for real-time guidance in avatar based physical therapy training system. | Dennis Shen, Yao Lu, Sujit Dey |
| 2015 | ISM | A Joint Asymmetric Graphics Rendering and Video Encoding Approach for Optimizing Cloud Mobile 3D Display Gaming User Experience. | Yao Liu, Yao Liu, Sujit Dey |
| 2015 | PIMRC | Renewable energy-aware video download in cellular networks. | Po-Han Chiang, Ranjini Guruprasad, Sujit Dey |
| 2014 | DAC | Variation Aware Cache Partitioning for Multithreaded Programs. | Vivek Joy Kozhikkottu, Abhisek Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan |
| 2014 | ISLPED | Variation tolerant design of a vector processor for recognition, mining and synthesis. | Vivek Joy Kozhikkottu, Swagath Venkataramani, Sujit Dey, Anand Raghunathan |
| 2014 | MSWIM | Mobile device video caching to improve video qoe and cellular network capacity. | Hasti A. Pedersen, Sujit Dey |
| 2014 | WWW | Construction of tag ontological graphs by locally minimizing weighted average hops. | Chetan Kumar Verma, Vijay Mahadevan, Nikhil Rasiwasia, Gaurav Aggarwal, Ravi Kant, Alejandro Jaimes, Sujit Dey |
| 2013 | WCNC | Adaptive Bit Rate capable video caching and scheduling. | Hasti Ahlehagh, Sujit Dey |
| 2013 | WCNC | Rate adaptation and base station reconfiguration for battery efficient video download. | Ranjini Guruprasad, Sujit Dey |
| 2013 | WCNC | QoS-aware dynamic cell reconfiguration for energy conservation in cellular networks. | Kyuho Son, Santosh V. Nagaraj, Mahasweta Sarkar, Sujit Dey |
| 2012 | DAC | Recovery-based design for variation-tolerant SoCs. | Vivek Joy Kozhikkottu, Sujit Dey, Anand Raghunathan |
| 2012 | WCNC | Video caching in Radio Access Network: Impact on delay and capacity. | Hasti Ahlehagh, Sujit Dey |
| 2011 | DATE | VESPA: Variability emulation for System-on-Chip performance analysis. | Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey |
| 2010 | GLOBECOM | Rendering Adaptation to Address Communication and Computation Constraints in Cloud Mobile Gaming. | Shaoxuan Wang, Sujit Dey |
| 2010 | WCNC | Addressing Response Time and Video Quality in Remote Server Based Internet Mobile Gaming. | Shaoxuan Wang, Sujit Dey |
| 2009 | GLOBECOM | Modeling and Characterizing User Experience in a Cloud Server Based Mobile Gaming Approach. | Shaoxuan Wang, Sujit Dey |
| 2009 | VLSID | Coping with Variations through System-Level Design. | Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy |
| 2007 | DAC | System-on-Chip Power Management Considering Leakage Power Variations. | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2007 | GLOBECOM | Joint Computation and Communication Scheduling to Enable Rich Mobile Applications. | Shoubhik Mukhopadhyay, Curt Schurgers, Sujit Dey |
| 2007 | ICCD | Modeling soft error effects considering process variations. | Chong Zhao, Sujit Dey |
| 2007 | PIMRC | A Device and Network-Aware Scaling Framework for Efficient Delivery of Scalable Video over Wireless Networks. | Naomi Ramos, Sujit Dey |
| 2006 | DATE | Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2006 | ISLPED | Considering process variations during system-level power analysis. | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2006 | ITC | Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits. | Chong Zhao, Sujit Dey |
| 2005 | DAC | FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2005 | DAC | Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. | Chong Zhao, Yi Zhao, Sujit Dey |
| 2005 | ITC | A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits. | Chong Zhao, Xiaoliang Bai, Sujit Dey |
| 2005 | WCNC | Dynamic end-to-end image adaptation for guaranteed quality of service in wireless image data services. | Dong-Gi Lee, Sujit Dey |
| 2004 | DAC | A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. | Chong Zhao, Xiaoliang Bai, Sujit Dey |
| 2004 | GLOBECOM | VSHAPER: an efficient method of serving video streams shaped for diverse wireless communication conditions. | Clark N. Taylor, Sujit Dey |
| 2004 | PIMRC | Dynamic image adaptation technique and architecture to enhance server performance in wireless image services. | Dong-Gi Lee, Sujit Dey |
| 2004 | PIMRC | CHASER: content and channel aware object scheduling and error control for wireless Web access in 3G networks. | Debashis Panigrahi, Sujit Dey |
| 2004 | WCNC | Data aware, low cost error correction for wireless sensor networks. | Shoubhik Mukhopadhyay, Debashis Panigrahi, Sujit Dey |
| 2004 | VLSID | Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
| 2004 | SECON | Model based error correction for wireless sensor networks. | Shoubhik Mukhopadhyay, Debashis Panigrahi, Sujit Dey |
| 2003 | DAC | A scalable software-based self-test methodology for programmable processors. | Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey |
| 2003 | ICCAD | Dynamic Platform Management for Configurable Platform-Based System-on-Chips. | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
| 2003 | IOLTS | Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC. | Yi Zhao, Sujit Dey |
| 2003 | ITC | HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. | Xiaoliang Bai, Sujit Dey, Angela Krstic |
| 2003 | VLSID | High-level Synthesis of Multi-process Behavioral Descriptions. | Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey |
| 2002 | DAC | Software-based diagnosis for processors. | Li Chen, Sujit Dey |
| 2002 | DAC | Embedded software-based self-testing for SoC design. | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
| 2002 | DAC | Communication architecture based power management for battery efficient system design. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2002 | ITC | On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. | Yi Zhao, Li Chen, Sujit Dey |
| 2002 | VLSID | Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi |
| 2002 | VLSID | Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). | Luciano Lavagno, Sujit Dey, Rajesh K. Gupta |
| 2002 | VLSID | A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. | Debashis Panigrahi, Clark N. Taylor, Sujit Dey |
| 2002 | VTS | Validation and Test of Network Processors and ASICs. | C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim |
| 2002 | VTS | LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. | Krishna Sekar, Sujit Dey |
| 2001 | DAC | Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. | Li Chen, Xiaoliang Bai, Sujit Dey |
| 2001 | DAC | On-Chip Communication Architecture for OC-768 Network Processors. | Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. Rao |
| 2001 | DAC | Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. | Clark N. Taylor, Sujit Dey, Yi Zhao |
| 2001 | VLSID | Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2001 | VLSID | Battery Life Estimation of Mobile Embedded Systems. | Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla Fabiana Chiasserini, Anand Raghunathan |
| 2001 | VLSID | Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. | Anand Raghunathan, Sujit Dey |
| 2001 | VTS | High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. | Xiaoliang Bai, Sujit Dey |
| 2000 | DAC | Self-test methodology for at-speed test of crosstalk in chip interconnects. | Xiaoliang Bai, Sujit Dey, Janusz Rajski |
| 2000 | DAC | Embedded hardware and software self-testing methodologies for processor cores. | Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng |
| 2000 | DAC | Test challenges for deep sub-micron technologies. | Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy |
| 2000 | DAC | Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey |
| 2000 | DATE | Efficient Power Co-Estimation Techniques for System-on-Chip Design. | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
| 2000 | ICCAD | Efficient Exploration of the SoC Communication Architecture Design Space. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2000 | ICCAD | Test of Future System-on-Chips. | Yervant Zorian, Sujit Dey, Mike Rodgers |
| 2000 | ITC | Analysis of interconnect crosstalk defect coverage of test sets. | Yi Zhao, Sujit Dey |
| 2000 | VLSID | Performance Analysis of Systems with Multi-Channel Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2000 | VTS | DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. | Li Chen, Sujit Dey |
| 1999 | DAC | Common-Case Computation: A High-Level Technique for Power and Performance Optimization. | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey |
| 1999 | ICCAD | Fault modeling and simulation for crosstalk in system-on-chip interconnects. | Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao |
| 1999 | ICCAD | Fast performance analysis of bus-based system-on-chip communication architectures. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 1999 | VLSID | Low Power Design Methodologies for Systems-on-Chips. | Kaushik Roy, Anand Raghunathan, Sujit Dey |
| 1998 | ASPDAC | Considering Testability during High-level Design (Embedded Tutorial). | Sujit Dey, Anand Raghunathan, Rabindra K. Roy |
| 1998 | DAC | A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. | Indradeep Ghosh, Sujit Dey, Niraj K. Jha |
| 1998 | ICCAD | High-level design validation and test. | Sujit Dey, Jacob A. Abraham, Yervant Zorian |
| 1998 | ICCAD | Transforming control-flow intensive designs to facilitate power management. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
| 1998 | ITC | Testing embedded-core based system chips. | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
| 1998 | VLSID | A Power Management Methodology for High-Level Synthesis. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
| 1998 | VLSID | Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. | Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
| 1997 | DAC | Power Management Techniques for Control-Flow Intensive Designs. | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
| 1997 | DATE | An RTL methodology to enable low overhead combinational testing. | Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta |
| 1997 | ICCAD | Performance analysis of a system of communicating processes. | Sujit Dey, Surendra Bommu |
| 1997 | ITC | H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. | Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey |
| 1997 | ITC | A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. | Indradeep Ghosh, Niraj K. Jha, Sujit Dey |
| 1996 | DAC | Glitch Analysis and Reduction in Register Transfer Level. | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | DAC | High-Level Synthesis for Testability: A Survey and Perspective. | Kenneth D. Wagner, Sujit Dey |
| 1996 | ICCAD | Register-transfer level estimation techniques for switching activity and power consumption. | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | ISLPED | Controller re-specification to minimize switching activity in controller/data path circuits. | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
| 1996 | VTS | H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. | Subhrajit Bhattacharya, Sujit Dey |
| 1995 | ASPDAC | Synthesis-for-testability using transformations. | Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy |
| 1995 | ICCAD | A controller-based design-for-testability technique for controller-data path circuits. | Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
| 1995 | ICCAD | Design-for-debugging of application specific designs. | Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi |
| 1994 | DAC | Clock Period Optimization During Resource Sharing and Assignment. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1994 | DAC | Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1994 | DAC | Resynthesis and Retiming for Optimum Partial Scan. | Srimat T. Chakradhar, Sujit Dey |
| 1994 | DAC | Optimizing Resource Utilization and Testability Using Hot Potato Techniques. | Miodrag Potkonjak, Sujit Dey |
| 1994 | ICASSP | Behavioral synthesis of low-cost partial scan designs for DSP applications. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1994 | ICCAD | Provably correct high-level timing analysis without path sensitization. | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
| 1994 | ICCAD | Non-scan design-for-testability of RT-level data paths. | Sujit Dey, Miodrag Potkonjak |
| 1994 | ITC | Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. | Sujit Dey, Miodrag Potkonjak |
| 1994 | VTS | Retiming sequential circuits to enhance testability. | Sujit Dey, Srimat T. Chakradhar |
| 1994 | VTS | Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1993 | DAC | Sequential Circuit Delay optimization Using Global Path Delays. | Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler |
| 1993 | DAC | Critical Path Minimization Using Retiming and Algebraic Speed-Up. | Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker |
| 1993 | ICCAD | Exploiting hardware sharing in high-level synthesis for partial scan optimization. | Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy |
| 1993 | ICCD | High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques. | Miodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker |
| 1992 | ICCAD | Exploiting multi-cycle false paths in the performance optimization of sequential circuits. | Pranav Ashar, Sujit Dey, Sharad Malik |
| 1992 | ICCAD | Performance optimization of sequential circuits by eliminating retiming bottlenecks. | Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler |
| 1991 | ICCD | Partitioning Sequential Circuits for Logic Optimization. | Sujit Dey, Franc Brglez, Gershon Kedem |
| 1990 | DAC | Corolla Based Circuit Partitioning and Resynthesis. | Sujit Dey, Franc Brglez, Gershon Kedem |