Sying-Jyan Wang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
34
Venues
10
Active years
1991–2025
Best venue rank
A*
Where they publish
Papers
34 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | Masking Based Protection Mechanism for Ascon against CPA Attack. | Sying-Jyan Wang, Ho Lam Cheung, Katherine Shu-Min Li |
| 2025 | ISCAS | Design of Reliable and Modeling-Attack Resistant Strong PUFs for Lightweight Applications. | Sying-Jyan Wang, Gong-Chi Wang, Chi-Yun Chen, Katherine Shu-Min Li |
| 2023 | ITC | Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. | Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho |
| 2022 | ASPDAC | Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. | Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho |
| 2022 | ETS | Trojan Insertions of Fully Programmable Valve Arrays. | Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho |
| 2022 | ITC | Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. | Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai |
| 2022 | ITC | Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. | Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang |
| 2021 | DATE | Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. | Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho |
| 2021 | ETS | Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. | Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu |
| 2021 | ITC | Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. | Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu |
| 2021 | ITC | WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. | Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou |
| 2020 | DATE | Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. | Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen |
| 2020 | ETS | PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. | Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, Gus Chang-Hung Han |
| 2020 | ITC | TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. | Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee |
| 2020 | VTS | Innovative Practice on Wafer Test Innovations. | Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang |
| 2019 | DAC | Adversarial Attack against Modeling Attack on PUFs. | Sying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li |
| 2019 | ITC | TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. | Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee |
| 2018 | ISCAS | Register PUF with No Power-Up Restrictions. | Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li |
| 2016 | ASPDAC | Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. | Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho |
| 2016 | VTS | Test and diagnosis of paper-based microfluidic biochips. | Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho |
| 2014 | ISCAS | Fast and accurate statistical static timing analysis. | Sying-Jyan Wang, Tsung-Huei Tzeng, Katherine Shu-Min Li |
| 2013 | ISCAS | Synthesis of 3D clock tree with pre-bond testability. | Sying-Jyan Wang, Cheng-Hao Lin, Katherine Shu-Min Li |
| 2012 | ISCAS | Low-power delay test architecture for pre-bond test. | Sying-Jyan Wang, Han-Hsuan Hsu, Katherine Shu-Min Li |
| 2009 | ISCAS | Level Converting Scan Flip-flops. | Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang |
| 2009 | ISCAS | Low Peak Power ATPG for n-Detection Test. | Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li |
| 2008 | ISCAS | Design and analysis of skewed-distribution scan chain partition for improved test data compression. | Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li |
| 2007 | DATE | High-level test synthesis for delay fault testability. | Sying-Jyan Wang, Tung-Hua Yeh |
| 2007 | ISCAS | Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. | Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li |
| 2005 | ISCAS | Low power parallel multiplier with column bypassing. | Mingchen Wen, Sying-Jyan Wang, Yen-Nan Lin |
| 2002 | ISLPED | Retiming-based logic synthesis for low-power. | Yu-Lung Hsu, Sying-Jyan Wang |
| 2001 | DAC | Generating Efficient Tests for Continuous Scan. | Sying-Jyan Wang, Sheng-Nan Chiou |
| 1997 | ICCAD | Test and diagnosis of fault logic blocks in FPGAs. | Sying-Jyan Wang, Tsi-Ming Tsai |
| 1992 | ICCD | Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. | Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka |
| 1991 | ICCD | Design and Synthesis of Self-Checking VLSI Circuits and Systems. | Niraj K. Jha, Sying-Jyan Wang |