| 2014 | ITC | Interposer test: Testing PCBs that have shrunk 100x. | T. M. Mak |
| 2014 | VTS | Innovative practices session 3C: Solving today's test challenges. | John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar |
| 2013 | VTS | Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters. | Jae Woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak |
| 2009 | ICCAD | Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. | Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak |
| 2009 | ITC | An industrial case study for X-canceling MISR. | Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak |
| 2008 | ITC | Jitters in high performance microprocessors. | T. M. Mak |
| 2007 | IOLTS | Infant Mortality--The Lesser Known Reliability Issue. | T. M. Mak |
| 2007 | IOLTS | Design for Resilience to Soft Errors and Variations. | Ming Zhang, T. M. Mak, James W. Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu |
| 2007 | ITC | Novel compensation scheme for local clocks of high performance microprocessors. | Cecilia Metra, Martin Omaa, T. M. Mak, Simon Tam |
| 2007 | VTS | Novel Approach to Clock Fault Testing for High Performance Microprocessors. | Cecilia Metra, Martin Omaa, T. M. Mak, Simon Tam |
| 2006 | DDECS | Can Clock Faults be Detected Through Functional Test? | Cecilia Metra, Daniele Rossi, Martin Omaa, Jos Manuel Cazeaux, T. M. Mak |
| 2006 | IOLTS | Test Challenges for 3D Circuits. | T. M. Mak |
| 2006 | IOLTS | Should Logic SER be Solved at the Circuit Level? | T. M. Mak, Subhasish Mitra |
| 2006 | IOLTS | Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. | Cecilia Metra, Martin Omaa, Daniele Rossi, Jos Manuel Cazeaux, T. M. Mak |
| 2006 | VLSID | Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak |
| 2005 | IOLTS | Does It Mean Less Testing for Self Calibrating Design?. | T. M. Mak |
| 2005 | IOLTS | DFT Assisted Built-In Soft Error Resilience. | T. M. Mak, Subhasish Mitra, Ming Zhang |
| 2005 | ITC | Logic soft errors: a major barrier to robust platform design. | Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim |
| 2005 | VTS | On Silicon-Based Speed Path Identification. | Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak |
| 2004 | DAC | On path-based learning and its applications in delay test and diagnosis. | Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir |
| 2004 | DATE | Are Our Design for Testability Features Fault Secure? | Cecilia Metra, T. M. Mak, Martin Omaa |
| 2004 | ICCAD | A path-based methodology for post-silicon timing validation. | Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng |
| 2004 | IOLTS | Testing of Hard Faults in Simultaneous Multithreaded Processors. | Eric F. Weglarz, Kewal K. Saluja, T. M. Mak |
| 2004 | ITC | Trends in manufacturing test methods and their implications. | Sandip Kundu, T. M. Mak, Rajesh Galivanche |
| 2004 | ITC | Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. | Cecilia Metra, T. M. Mak, Martin Omaa |
| 2004 | ITC | Elimination of Traditional Functional Testing of Interface Timings at Intel. | Mike Tripp, T. M. Mak, Anne Meixner |
| 2003 | DAC | Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak |
| 2003 | ITC | Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak |
| 2003 | ITC | Elimination of Traditional Functional Testing of Interface Timings at Intel. | Mike Tripp, T. M. Mak, Anne Meixner |
| 2003 | VTS | Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. | Kaushik Roy, T. M. Mak, Kwang-Ting Cheng |
| 2002 | ITC | Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. | Cecilia Metra, Stefano Di Francescantonio, T. M. Mak |
| 2001 | ITC | Crosstalk test generation on pseudo industrial circuits: a case study. | Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer |
| 1998 | ITC | Cache RAM inductive fault analysis with fab defect modeling. | T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu |