| 2025 | ACNS | Arithmetic Masking Countermeasure to Mitigate Side-Channel-Based Model Extraction Attack on DNN Accelerator. | Hirokatsu Yamasaki, Kota Yoshida, Yuta Fukuda, Takeshi Fujino |
| 2024 | ACNS | Incorporating Cluster Analysis of Feature Vectors for Non-profiled Deep-learning-Based Side-Channel Attacks. | Yuta Fukuda, Kota Yoshida, Takeshi Fujino |
| 2024 | ACNS | FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. | Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino |
| 2024 | ACNS | Model Extraction Attack Without Natural Images. | Kota Yoshida, Takeshi Fujino |
| 2022 | ACNS | Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs. | Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino |
| 2021 | ACNS | Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments. | Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino |
| 2021 | ACNS | Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment. | Kota Yoshida, Takeshi Fujino |
| 2021 | CCS | Practical Aspects on Non-profiled Deep-learning Side-channel Attacks against AES Software Implementation with Two Types of Masking Countermeasures including RSM. | Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino |
| 2021 | CCS | Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. | Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino |
| 2021 | MICRO | Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code. | Kota Yoshida, Kuniyasu Suzaki, Takeshi Fujino |
| 2020 | CCS | Exploring Effect of Residual Electric Charges on Cryptographic Circuits. | Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino |
| 2020 | CCS | Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks. | Kota Yoshida, Takeshi Fujino |
| 2020 | ISCAS | Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. | Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino |
| 2020 | ISCAS | Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. | Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino |
| 2019 | CCS | Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. | Mitsuru Shiozaki, Takeshi Fujino |
| 2019 | DSD | Deep Learning Side-Channel Attack Against Hardware Implementations of AES. | Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino |
| 2019 | FCCM | Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. | Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino |
| 2015 | ISCAS | Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. | Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino |
| 2014 | CHES | Reversing Stealthy Dopant-Level Circuits. | Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino |
| 2014 | ISCAS | Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. | Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino |
| 2014 | ISCAS | Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection. | Yuki Yanagihara, Toshiya Honda, Takeshi Kumaki, Takeshi Fujino |
| 2013 | CHES | On Measurable Side-Channel Leaks Inside ASIC Design Primitives. | Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino |
| 2013 | FPGA | Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). | Anh-Tuan Hoang, Takeshi Fujino |
| 2012 | DSD | Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. | Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino |
| 2012 | FPGA | Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. | Anh-Tuan Hoang, Takeshi Fujino |
| 2011 | ISCAS | The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. | Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino |
| 2010 | CAINE | Placement Tool Dedicated for a Via-programmable Logic Device VPEX. | Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino |