| 2006 | VLSID | Reducing Design Verification Cycle Time through Testbench Redundancy. | Aman Kokrady, Theo J. Powell, S. Ramakrishnan |
| 2005 | ITC | Chasing subtle embedded RAM defects for nanometer technologies. | Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee |
| 2003 | ITC | BIST for Deep Submicron ASIC Memories with High Performance Application. | Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai |
| 2000 | VTS | Delta Iddq for Testing Reliability. | Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce |
| 1997 | ITC | A 256Meg SDRAM BIST for Disturb Test Application. | Theo J. Powell, Dan Cline, Francis Hii |
| 1996 | ITC | Correlating Defects to Functional and I | Theo J. Powell, James R. Pair, Bernard G. Carbajal III |
| 1996 | VTS | Consistently dominant fault model for tristate buffer nets. | Theo J. Powell |
| 1995 | ITC | Test Generation and Design for Test for a Large Multiprocessing DSP. | Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell |
| 1994 | VTS | Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]. | Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry |
| 1988 | ITC | Testability Features in the TMS370 Family of Microcomputers. | Theo J. Powell, Fred Hwang, Bill Johnson |
| 1982 | ITC | Analysis and Simulation of Parallel Signature Analyzers. | Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte |
| 1982 | ITC | An Architecture for Testable VLSI Processors. | Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell |