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Timo D. Hmlinen

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

83

Venues

21

Active years

2000–2026

Best venue rank

C

Where they publish

Papers

83 indexed papers, newest first.

YearVenueTitleAuthors
2026RTASWork in Progress: Hardware Support for EDF Scheduling on Bare-Metal Systems.Antti Nurmi, Justin Beaurivage, Pawel Dzialo, Per Lindgren, Timo D. Hmlinen
2024DDECSAn Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA.Sakari Lahti, Tuomas Aaltonen, Elizaveta Rastorgueva-Foi, Jukka Talvitie, Bo Tan, Timo D. Hmlinen
2023DSDAnTiQ: A Hardware-Accelerated Priority Queue Design with Constant Time Arbitrary Element Removal.Antti Nurmi, Per Lindgren, Thomas Szymkowiak, Timo D. Hmlinen
2022DSDA Resilient System Design to Boot a RISC-V MPSoC.Antti Nurmi, Antti Rautakoura, Henri Lunnikivi, Timo D. Hmlinen
2021IECONA Survey on System-on-a-Chip Design Using Chisel HW Construction Language.Matti Kyr, Timo D. Hmlinen
2020DSDKamel: IP-XACT compatible intermediate meta-model for IP generation.Antti Rautakoura, Matti Kyr, Timo D. Hmlinen, Wolfgang Ecker, Esko Pekkarinen, Mikko Teuho
2020ISCASImplementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis.Sakari Lahti, Pablo Pascual Campo, Vesa Lampu, Lauri Anttila, Mikko Valkama, Timo D. Hmlinen
2019VCIPVisualization of Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud.Panu Sjvall, Mikko Teuho, Arto Oinonen, Jarno Vanne, Timo D. Hmlinen
2018DCCRate-Distortion-Complexity Optimized Coding Scheme for Kvazaar HEVC Intra Encoder.Ari Lemmetti, Eemeli Kallio, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen
2018DSDModeling RISC-V Processor in IP-XACT.Esko Pekkarinen, Timo D. Hmlinen
2018DSDVisualization of Memory Map Information in Embedded System Design.Mikko Teuho, Esko Pekkarinen, Timo D. Hmlinen
2018DSDFeasibility of FPGA Accelerated IPsec on Cloud.Markku Vajaranta, Vili Viitamki, Arto Oinonen, Timo D. Hmlinen, Ari Kulmala, Jouni Markunmki
2018ICDCSLow Latency Edge Rendering Scheme for Interactive 360 Degree Virtual Reality Gaming.Marko Viitanen, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala
2018ISCASFPGA-Powered 4K120p HEVC Intra Encoder.Panu Sjvall, Vili Viitamki, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala
2018ISCASLive Demonstration: 4K100p HEVC Intra Encoder.Vili Viitamki, Panu Sjvall, Jarno Vanne, Timo D. Hmlinen, Ari Kulmala
2018ISMLive Demonstration: Kvazzup 4K HEVC Video Call.Joni Rasanen, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen
2018ISMOpen framework for error-compensated gaze data collection with eye tracking glasses.Kari Siivonen, Joose Sainio, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen
2017ICASSPHigh-level synthesis implementation of HEVC 2-D DCT/DST on FPGA.Panu Sjovall, Vili Viitamki, Jarno Vanne, Timo D. Hmlinen
2017INDINComplexity based test cases for log file analyzers.Esa Heikkinen, Timo D. Hmlinen
2017ISCASHigh-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA.Vili Viitamki, Panu Sjovall, Jarno Vanne, Timo D. Hmlinen
2017ISMKvazzup: Open Software for HEVC Video Calls.Joni Rasanen, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen
2017ISMKvazaar: HEVC/H.265 4K30p Intra Encoder.Arttu Yl-Outinen, Ari Lemmetti, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen
2016ICIPAVX2-optimized Kvazaar HEVC intra encoder.Ari Lemmetti, Ari Koivula, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen
2016IECONBehavior Mining Language for mining expected behavior from log files.Esa Heikkinen, Timo D. Hmlinen
2016IECONDesigning a clock cycle accurate application with high-level synthesis.Sakari Lahti, Jarno Vanne, Timo D. Hmlinen
2016ISCASLive demonstration: Run-time visualization of Kvazaar HEVC intra encoder.Marko Viitanen, Ari Koivula, Jarno Vanne, Timo D. Hmlinen
2016ISMRTP/RTCP Reception Hint Tracks for Video Call Recording and Playback.Joni Rasanen, Marko Viitanen, Jarno Vanne, Timo D. Hmlinen, Miska M. Hannuksela, Vinod Kumar Malamal Vadakital
2016PROFESLog File Analyzing in Intelligent Transportation Systems Development.Esa Heikkinen, Timo D. Hmlinen
2016PROFESPROMOTE: A Process Mining Tool for Embedded System Development.Arttu Leppkoski, Timo D. Hmlinen
2015DSDHigh-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA.Panu Sjovall, Janne Virtanen, Jarno Vanne, Timo D. Hmlinen
2015IECONResolving parameter reference management in IP-XACT using Kactus2.Esko Pekkarinen, Mikko Teuho, Erno Salminen, Timo D. Hmlinen
2015ISCASKvazaar HEVC encoder for efficient intra coding.Marko Viitanen, Ari Koivula, Ari Lemmetti, Jarno Vanne, Timo D. Hmlinen
2015VCIPKvazaar HEVC still image coding on Raspberry Pi 2 for low-cost remote surveillance.Marko Viitanen, Ari Koivula, Jarno Vanne, Timo D. Hmlinen
2014VCIPComparative study of 8 and 10-bit HEVC encoders.Jarno Vanne, Marko Viitanen, Ari Koivula, Timo D. Hmlinen
2012ISCASComplexity analysis of next-generation HEVC decoder.Marko Viitanen, Jarno Vanne, Timo D. Hmlinen, Moncef Gabbouj, Jani Lainema
2011DSDKactus2: Environment for Embedded Product Development Using IP-XACT and MCAPI.Antti Kamppi, Lauri Matilainen, Joni-Matti Mtt, Erno Salminen, Timo D. Hmlinen, Marko Hnnikinen
2011GPCLink Quality-Based Channel Selection for Resource Constrained WSNs.Markku Hnninen, Jukka Suhonen, Timo D. Hmlinen, Marko Hnnikinen
2009DATEEvaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA.Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo D. Hmlinen, Marko Hnnikinen
2007DATECompact hardware design of Whirlpool hashing core.Timo Alho, Panu Hmlinen, Marko Hnnikinen, Timo D. Hmlinen
2007DATECost-aware capacity optimization in dynamic multi-hop WSNs.Jukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, Marko Hnnikinen, Timo D. Hmlinen
2007DDECSInstruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.Ari Kulmala, Erno Salminen, Timo D. Hmlinen
2007DDECSIP Integration Overhead Analysis in System-on-Chip Video Encoder.Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hmlinen
2007DSDEvaluating the Model Accuracy in Automated Design Space Exploration.Kalle Holma, Mikko Setl, Erno Salminen, Timo D. Hmlinen
2007DSDOn network-on-chip comparison.Erno Salminen, Ari Kulmala, Timo D. Hmlinen
2007FDLModeling Embedded Software Platforms with a UML Profile.Tero Arpinen, Mikko Setl, Petri Kukkala, Erno Salminen, Marko Hnnikinen, Timo D. Hmlinen
2006DATEConfigurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications.Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hnnikinen, Timo D. Hmlinen
2006DDECSParallel Memory Architecture for Arbitrary Stride Accesses.Eero Aho, Jarno Vanne, Timo D. Hmlinen
2006DDECSImpact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder.Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hmlinen, Marko Hnnikinen
2006DSDDesign and Implementation of Low-Area and Low-Power AES Encryption Hardware Core.Panu Hmlinen, Timo Alho, Marko Hnnikinen, Timo D. Hmlinen
2006DSDComparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA.Ari Kulmala, Timo D. Hmlinen, Marko Hnnikinen
2006FPLReliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.Ari Kulmala, Timo D. Hmlinen, Marko Hnnikinen
2006MOBIHOCHigh-performance multi-radio WSN platform.Mikko Kohvakka, Tero Arpinen, Marko Hnnikinen, Timo D. Hmlinen
2006PIMRCWSN API: Application Programming Interface for Wireless Sensor Networks.Jari K. Juntunen, Mauri Kuorilehto, Mikko Kohvakka, Ville Kaseva, Marko Hnnikinen, Timo D. Hmlinen
2006PIMRCTransmission Power Based Path Loss Metering for Wireless Sensor Networks.Mikko Kohvakka, Jukka Suhonen, Marko Hnnikinen, Timo D. Hmlinen
2006PIMRCConfigurable Protocol Engine for Runtime-Configurable Communication Subsystems on Multiprocessor SoC.Petri Kukkala, Marko Hnnikinen, Timo D. Hmlinen
2006PIMRCExperimenting TCP/IP for Low-Power Wireless Sensor Networks.Mauri Kuorilehto, Jukka Suhonen, Mikko Kohvakka, Marko Hnnikinen, Timo D. Hmlinen
2006PIMRCCost-Aware Dynamic Routing Protocol for Wireless Sensor Networks - Design and Prototype Experiments.Jukka Suhonen, Mauri Kuorilehto, Marko Hnnikinen, Timo D. Hmlinen
2006QshineEvaluation of throughput estimation models and algorithms for WLAN frequency planning.Timo Vanhatupa, Marko Hnnikinen, Timo D. Hmlinen
2005DATEUML 2.0 Profile for Embedded System Design.Petri Kukkala, Jouni Riihimki, Marko Hnnikinen, Timo D. Hmlinen, Klaus Kronlf
2005DSDDesign of Transport Triggered Architecture Processors for Wireless Encryption.Panu Hmlinen, Jari Heikkinen, Marko Hnnikinen, Timo D. Hmlinen
2005DSDWireless Sensor Network Implementation for Industrial Linear Position Metering.Mikko Kohvakka, Marko Hnnikinen, Timo D. Hmlinen
2005DSDCo-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL.Petri Kukkala, Marko Hnnikinen, Timo D. Hmlinen
2005FPLA Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC.Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hnnikinen, Timo D. Hmlinen
2005ISCASAlgorithmic optimization of H.264/AVC encoder.Juho Lahti, Jari K. Juntunen, Olli Lehtoranta, Timo D. Hmlinen
2005ISCASHIBI-based multiprocessor SoC on FPGA.Erno Salminen, Ari Kulmala, Timo D. Hmlinen
2005LANMANSoftware and hardware prototypes of the IEEE 1588 precision time protocol on wireless LAN.Juha Kannisto, Timo Vanhatupa, Marko Hnnikinen, Timo D. Hmlinen
2005LANMANFrequency management tool for multi-cell WLAN performance optimization.Timo Vanhatupa, Marko Hnnikinen, Timo D. Hmlinen
2005PIMRCUltra low energy wireless temperature sensor network implementation.Mikko Kohvakka, Marko Hnnikinen, Timo D. Hmlinen
2005PIMRCEnergy optimized beacon transmission rate in a wireless sensor network.Mikko Kohvakka, Marko Hnnikinen, Timo D. Hmlinen
2005PIMRCA middleware for task allocation in wireless sensor networks.Mauri Kuorilehto, Marko Hnnikinen, Timo D. Hmlinen
2005PIMRCMultihop IEEE 802.11b WLAN Performance for VoIP.Timo Vanhatupa, Marko Hnnikinen, Timo D. Hmlinen
2004PIMRCUML 2.0 implementation of an embedded WLAN protocol.Petri Kukkala, Vin Helminen, Marko Hnnikinen, Timo D. Hmlinen
2003DSDDistributing SoC Simulations over a Network of Computers.Jouni Riihimki, Vin Helminen, Kimmo Kuusilinna, Timo D. Hmlinen
2003ISCASComparison of synthesized bus and crossbar interconnection architectures.Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hmlinen
2003PIMRCPositioning with IEEE 802.11b wireless LAN.Antti Kotanen, Marko Hnnikinen, Helena Leppkoski, Timo D. Hmlinen
2003PIMRCClass of service control protocol for wireless LAN.Jukka Suhonen, Marko Hnnikinen, Timo D. Hmlinen
2002DSDEnhanced Configurable Parallel Memory Architecture.Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hmlinen
2001ICASSPPerformance analysis of low bit rate H.26L video encoder.Antti Hallapuro, Ville Lappalainen, Timo D. Hmlinen
2001ICASSPConfigurable hardware implementation of triple-DES encryption algorithm for wireless local area network.Panu Hmlinen, Marko Hnnikinen, Timo D. Hmlinen, Jukka Saarinen
2001ISCASInterfacing multiple processors in a system-on-chip video encoder.Erno Salminen, Timo D. Hmlinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen
2000ISCASParallel DSP implementation of wavelet transform in image compression.Kaisa Haapala, Pasi Kolinummi, Timo D. Hmlinen, Jukka Saarinen
2000ISCASScalable implementation of H.263 video encoder on a parallel DSP system.Pasi Kolinummi, Juha Sarkijarvi, Timo D. Hmlinen, Jukka Saarinen
2000ISCASReal-time H.263 encoding of QCIF-images on TMS320C6201 fixed point DSP.Olli Lehtoranta, Timo D. Hmlinen, Jukka Saarinen