| 2018 | ISCAS | A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. | Hiroki Nakahara, Tsutomu Sasao |
| 2017 | DATE | An algorithm to find optimum support-reducing decompositions for index generation functions. | Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi |
| 2015 | ETS | A soft-error tolerant TCAM using partial don't-care keys. | Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase |
| 2015 | FPL | A deep convolutional neural network based on nested residue number system. | Hiroki Nakahara, Tsutomu Sasao |
| 2013 | FPL | A packet classifier using LUT cascades based on EVMDDS (k). | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2013 | ICCD | A TCAM generator for packet classification. | Infall Syafalni, Tsutomu Sasao |
| 2012 | ASPDAC | Linear decomposition of index generation functions. | Tsutomu Sasao |
| 2012 | DATE | Row-shift decompositions for index generation functions. | Tsutomu Sasao |
| 2012 | ICA3PP | On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. | Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao |
| 2010 | DSD | A Packet Classifier Using a Parallel Branching Program Machine. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2010 | DSD | On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions. | Tsutomu Sasao |
| 2010 | MEMOCODE | A regular expression matching using non-deterministic finite automaton. | Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2009 | DSD | The Parallel Sieve Method for a Virus Scanning Engine. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura |
| 2009 | DSD | Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. | Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura |
| 2009 | FPL | A virus scanning engine using a parallel finite-input memory machine and MPUs. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura |
| 2008 | DSD | Programmable Numerical Function Generators for Two-Variable Functions. | Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao |
| 2008 | DSD | On the Complexity of Error Detection Functions for Redundant Residue Number Systems. | Tsutomu Sasao, Yukihiro Iguchi |
| 2008 | FPL | Numerical function generators using bilinear interpolation. | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
| 2008 | ICCAD | On the numbers of variables to represent sparse logic functions. | Tsutomu Sasao |
| 2007 | ASPDAC | Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
| 2007 | DSD | Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
| 2007 | DSD | An Implementation of an Address Generator Using Hash Memories. | Tsutomu Sasao, Munehiro Matsuura |
| 2006 | ASPDAC | Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
| 2006 | ASPDAC | A fast logic simulator using a look up table cascade emulator. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2005 | DAC | BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. | Tsutomu Sasao, Munehiro Matsuura |
| 2005 | DSD | On LUT Cascade Realizations of FIR Filters. | Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki |
| 2005 | FPL | Programmable Numerical Function Generators: Architectures and Synthesis Method. | Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler |
| 2004 | ASPDAC | Efficient computation of canonical form for Boolean matching in large libraries. | Debatosh Debnath, Tsutomu Sasao |
| 2004 | ASPDAC | Minimization of memory size for heterogeneous MDDs. | Shinobu Nagayama, Tsutomu Sasao |
| 2004 | ASPDAC | A fast method to derive minimum SOPs for decomposable functions. | Tsutomu Sasao, Jon T. Butler |
| 2004 | DAC | A method to decompose multiple-output logic functions. | Tsutomu Sasao, Munehiro Matsuura |
| 2003 | ASPDAC | Evaluation of multiple-output logic functions using decision diagrams. | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
| 2003 | DAC | Large-scale SOP minimization using decomposition and functional properties. | Alan Mishchenko, Tsutomu Sasao |
| 2001 | ASPDAC | On the minimization of SOPs for bi-decomposition functions. | Tsutomu Sasao, Jon T. Butler |
| 2001 | ICCD | Realization of Multiple-Output Functions by Reconfigurable Cascades. | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
| 2000 | ASPDAC | Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. | Debatosh Debnath, Tsutomu Sasao |
| 2000 | ASPDAC | A hardware simulation engine based on decision diagrams (short paper). | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno |
| 2000 | ASPDAC | Three parameters to find functional decompositions. | Tsutomu Sasao, Ken-ichi Kurimoto |
| 2000 | ITC | Selection of potentially testable path delay faults for test generation. | Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ASPDAC | Fast Boolean Matching Under Permutation Using Representative. | Debatosh Debnath, Tsutomu Sasao |
| 1999 | ASPDAC | Realization of Regular Ternary Logic Functions. | Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno |
| 1998 | ASPDAC | A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. | Debatosh Debnath, Tsutomu Sasao |
| 1998 | ASPDAC | Decision Diagrams for Discrete Functions: Classification and Unified Interpretation. | Radomir S. Stankovic, Tsutomu Sasao |
| 1997 | ASPDAC | An optimization of AND-OR-EXOR three-level networks. | Debatosh Debnath, Tsutomu Sasao |
| 1997 | ASPDAC | On properties of Kleene TDDs. | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
| 1995 | ASPDAC | GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. | Debatosh Debnath, Tsutomu Sasao |
| 1986 | DAC | MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators. | Tsutomu Sasao |