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Yibo Lin

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

128

Venues

15

Active years

2009–2026

Best venue rank

A*

Where they publish

Papers

128 indexed papers, newest first.

YearVenueTitleAuthors
2026ASPDACMOSTAR: Multi-Stage Hierarchical Bayesian Optimization for Substructure-Aware High-Dimensional Analog Circuit Sizing.Weijian Fan, Haoyi Zhang, Weibin Lin, Runsheng Wang, Yibo Lin
2026ASPDACStandard Cell Layout Synthesis for Dual-Sided 3D-Stacked Transistors.Kairong Guo, Haoran Lu, Rui Guo, Jiarui Wang, Chunyuan Zhao, Heng Wu, Runsheng Wang, Yibo Lin
2026ASPDACHeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support.Zizheng Guo, Haichuan Liu, Xizhe Shi, Shenglu Hua, Zuodong Zhang, Chunyuan Zhao, Runsheng Wang, Yibo Lin
2026ASPDACIR Drop-Aware ECO: A Fast Approach to Minimize Layout and Timing Disturbance.Jingchao Hu, Yibo Lin, Hao Yu, Quan Chen, Zhou Jin, Cheng Zhuo
2026ASPDACHeteroLatch: A CPU-GPU Heterogeneous Latch-Aware Timing Analysis Engine.Xizhe Shi, Zizheng Guo, Yibo Lin, Zuodong Zhang, Yun Liang, Runsheng Wang
2026ASPDACAC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models.Chenhao Xue, Kezhi Li, Jiaxing Zhang, Yi Ren, Zhengyuan Shi, Chen Zhang, Yibo Lin, Lining Zhang, Qiang Xu, Guangyu Sun
2026DATEDSR: A Systematic Approach for Efficient Double-sided Signal Routing.Jianqing Chen, Zhenkun Lin, Xun Jiang, Genggeng Liu, Yibo Lin, Gang Du
2026DATEProvably Optimal Planar Pareto Nearest Neighbor Search with Double Monotone Chains.Zizheng Guo, Runsheng Wang, Yibo Lin
2026DATEGRAIN: A Design-Intent-Driven Analog Layout Migration Framework.Bingyang Liu, Haoning Jiang, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, David Z. Pan, Yibo Lin
2026DATESubmodular Maximization-inspired Adaptive Routing Bend Space Planning.Siting Liu, Peng Xu, Peiyu Liao, Keren Zhu, Yibo Lin, Bei Yu
2026DATESONIC: Smart Optimization for Neural-Integrated CMP with Timing-Aware Fills.Jiajun Tan, Qichao Ma, Yiming Du, Yiming Gan, Ling Lang, Yibo Lin, Ming Zhu, Zongwei Wang, Yimao Cai
2026DATEEMaper: Cross-level Electromigration Aware Placement and Routing EDA Workflow for Interconnects Hotspot Prediction and Mitigation.Chenglin Ye, Yuze Lu, Yizhan Liu, Ligong Zhang, Jinghan Xu, Fei Liu, Yibo Lin, Zheng Zhou, Xiaoyan Liu
2026DATEEfficient Warpage Simulation of Complex 2.5-D/3-D IC Structures with Novel Meshing Algorithm and Layerwise Plate Theory.Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang
2026FPGATDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement.Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin
2025ASPDACPathGen: An Efficient Parallel Critical Path Generation Algorithm.Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
2025ASPDACExploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells.Kairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang, Yibo Lin
2025ASPDACiTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis.Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
2025DACRUPlace: Optimizing Routability via Unified Placement and Routing Formulation.Yifan Chen, Jing Mai, Zuodong Zhang, Yibo Lin
2025DACGEM: GPU-Accelerated Emulator-Inspired RTL Simulation.Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, Haoxing Ren
2025DACA Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025DACSynergistic Die-Level Router for Multi-FPGA System with Time-Division Multiplexing Optimization.Jiarui Wang, Yanjing Liu, Yibo Lin
2025DACSDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation.Ziyang Yu, Peng Xu, Zixiao Wang, Binwu Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Bei Yu, Martin D. F. Wong
2025DACG-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks.Lijie Zeng, Jiatai Sun, Xiao Wu, Dan Niu, Tianshi Wang, Yibo Lin, Zuochang Ye, Zhou Jin
2025DATESEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support.Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025DATEA Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals.Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2025DATEHandling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection.Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2025DATEMORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC.Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang
2025ICCADDifferentiable Physical Optimization.Yufan Du, Zizheng Guo, Runsheng Wang, Yibo Lin
2025ICCADDiffCCD: Differentiable Concurrent Clock and Data Optimization.Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, Bei Yu
2025ICCADIncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows.Haichuan Liu, Zizheng Guo, Runsheng Wang, Yibo Lin
2025ICCADGPU Acceleration for Versatile Buffer Insertion.Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu
2025ICCADOrthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization.Yi Ren, Baokang Peng, Chenhao Xue, Kairong Guo, Yukun Wang, Guoyao Cheng, Yibo Lin, Lining Zhang, Guangyu Sun
2025ICCADMMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs.Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025ICCADGTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection.Chunyuan Zhao, Jiarui Wang, Xun Jiang, Jincheng Lou, Yibo Lin
2025ICCADHigh-Resolution Full-Chip Thermal Resistance Extraction of BEOL Interconnects in 3-D ICs Considering Detailed Via Connectivity.Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang
2025ICMLDeepLayout: Learning Neural Representations of Circuit Placement Layout.Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Qiang Xu, Runsheng Wang, Yibo Lin
2025ISCASLayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction.Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024DACPowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning.Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2024DACPVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis.Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang
2024DACG-kway: Multilevel GPU-Accelerated k-way Graph Partitioner.Wan-Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu
2024DACLesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu
2024DACTop-Level Routing for Multiply-Instantiated Blocks with Topology Hashing.Jiarui Wang, Xun Jiang, Yibo Lin
2024DACOltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation.Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun
2024DACEasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration.Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024DATEHeterogeneous Static Timing Analysis with Advanced Delay Calculator.Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang
2024DATESAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios.Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024ICCADFusion of Global Placement and Gate Sizing with Differentiable Optimization.Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2024ICCADJoint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits.Xiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang
2024ICCADHeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis.Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang
2024ICCADMORPH: More Robust ASIC Placement for Hybrid Region Constraint Management.Jing Mai, Zuodong Zhang, Yibo Lin, Runsheng Wang, Ru Huang
2024ICCADATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC.Qipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang
2024ICCADHeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method.Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin
2024ICCADFaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects.Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang
2024ICLRCircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment.Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2024MICROHestia: An Efficient Cross-Level Debugger for High-Level Synthesis.Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang
2023ASPDACMacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy.Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin
2023ASPDACA Robust FPGA Router with Concurrent Intra-CLB Rerouting.Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin
2023DACGeneral-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang
2023DACOn a Moreau Envelope Wirelength Model for Analytical Global Placement.Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023DACConcurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023DACMTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line.Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, Ru Huang
2023DACLRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition.Yu Zhang, Yifan Chen, Zhonglin Xie, Hong Xu, Zaiwen Wen, Yibo Lin, Bei Yu
2023DACMitigating Distribution Shift for Congestion Optimization in Global Placement.Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023DATESAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang
2023DATEREAD: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang
2023ICCADStronger Mixed-Size Placement Backbone Considering Second-Order Information.Yifan Chen, Zaiwen Wen, Yun Liang, Yibo Lin
2023ICCADInvited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2023ICCADREAD: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang
2023IJCAIFastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023MICROKhronos: Fusing Memory Access for Improved Hardware RTL Simulation.Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang
2022ASPDACFPGA-Accelerated Maze Routing Kernel for VLSI Designs.Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang
2022ASPDACEfficient Critical Paths Search Algorithm using Mergeable Heap.Kexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2022DACDifferentiable-timing-driven global placement.Zizheng Guo, Yibo Lin
2022DACA timing engine inspired graph neural network model for pre-routing slack prediction.Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin
2022DACMulti-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility.Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin
2022DACLHNN: lattice hypergraph neural network for VLSI congestion prediction.Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng
2022DACAVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2022DATEDREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting.Peiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2022DATEFastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler.Siting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2022DATEMixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems.Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu
2022DATEEventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis.Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2022ICCADGPU-Accelerated Rectilinear Steiner Tree Generation.Zizheng Guo, Feng Gu, Yibo Lin
2022ICCADDeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography.Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang
2021ASPDACLayout Symmetry Annotation for Analog Circuits with Graph Neural Networks.Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin
2021ASPDACPhysical Synthesis for Advanced Neural Network Processors.Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu
2021ASPDACDeep Learning for Mask Synthesis and Verification: A Survey.Yibo Lin
2021DACInteractive Analog Layout Editing with Instant Placement Legalization.Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin
2021DACA Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2021DACGPU-accelerated Path-based Timing Analysis.Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
2021DACUltrafast CPU/GPU Kernels for Density Accumulation in Placement.Zizheng Guo, Jing Mai, Yibo Lin
2021DATETowards AQFP-Capable Physical Design Automation.Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin
2021DATEGlobal Placement with Deep Learning-Enabled Explicit Routability Optimization.Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu
2021DATEAsynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing.Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, Yayi Wei
2021ICCADHeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism.Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2021ICCADGPU-accelerated Critical Path Generation with Path Constraints.Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
2020ASPDACHigh-Definition Routing Congestion Prediction for Large-Scale FPGAs.Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan
2020ASPDACSMingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020DACAdaptive Layout Decomposition with Graph Embedding Neural Networks.Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu
2020ICCADDREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints.Jiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan
2020ICCADGPU-Accelerated Static Timing Analysis.Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2020ICCADGPU Acceleration in VLSI Back-end Design: Overview and Case Studies.Yibo Lin
2019AISTATSTowards a Theoretical Understanding of Hashing-Based Neural Nets.Yibo Lin, Zhao Song, Lin F. Yang
2019ASPDACSemi-supervised hotspot detection with self-paced multi-task learning.Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan
2019ASPDACTackling signal electromigration with learning-based detection and multistage mitigation.Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan
2019ASPDACLithoROC: lithography hotspot detection with explicit ROC optimization.Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan
2019DACGAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks.Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan
2019DACDREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan
2019DACWellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2019DACLithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks.Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan
2019DATELitho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, David Z. Pan
2019ICCADMixed Precision Neural Architecture Search for Energy Efficient Deep Learning.ChengYue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan
2019ICCADelfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs.Wuxi Li, Yibo Lin, David Z. Pan
2019ICCADMAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019ICCADGeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2018ASPDACLayout-dependent aging mitigation for critical path timing.Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan
2018ASPDACA practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion.Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2018ICMLLearning Long Term Dependencies via Fourier Recurrent Units.Jiong Zhang, Yibo Lin, Zhao Song, Inderjit S. Dhillon
2018ITCMachine Learning for Yield Learning and Optimization.Yibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan
2017DACConcurrent Pin Access Optimization for Unidirectional Routing.Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan
2017ICCDPatterning Aware Design Optimization of Selective Etching in N5 and Beyond.Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
2017ISLPEDPlacement mitigation techniques for power grid electromigration.Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan, David Z. Pan
2016ASPDACStitch aware detailed placement for multiple e-beam lithography.Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2016ICCADMrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes.Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016ICCADA novel unified dummy fill insertion framework with SQP-based optimization method.Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2015DACHigh performance dummy fill insertion with coupling and uniformity constraints.Yibo Lin, Bei Yu, David Z. Pan
2015DACPushing multiple patterning in sub-10nm: are we ready?David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin
2015ICCADTriple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2009ICTDCreating a mobile-phone based geographic surveillance system for avian influenza.Yibo Lin, Claire Heffernan