| 2025 | GECCO | Large Language Model Driven Evolutionary Optimization Benchmark Generation Algorithm. | Yuhiro Ono, Tomohiro Harada, Yukiya Miura |
| 2025 | SMC | How Reliable is Validation Accuracy for Estimating Surrogate Model Generalization in Surrogate-Assisted Evolutionary Algorithms? | Yuki Hanawa, Tomohiro Harada, Yukiya Miura |
| 2024 | CEC | Analysis of the Impact of Prediction Accuracy on Search Performance in Surrogate-assisted Evolutionary Algorithms. | Yuki Hanawa, Tomohiro Harada, Yukiya Miura |
| 2024 | IJCNN | Cooperative Autonomous Driving Control among Vehicles of Different Sizes Using Deep Reinforcement Learning. | Akito Takenaka, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matuoka |
| 2023 | GECCO | Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution. | Hitomi Kano, Tomohiro Harada, Yukiya Miura, Masahiro Kanazaki |
| 2021 | IOLTS | A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. | Yukiya Miura, Shingo Tsutsumi |
| 2020 | IOLTS | Soft Error Tolerance of Power-Supply-Noise Hardened Latches. | Yukiya Miura, Yuya Kinoshita |
| 2020 | IOLTS | On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. | Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura |
| 2020 | VTS | Innovative Test Practices in Asia. | Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama |
| 2019 | IOLTS | Development of FF Circuits for Measures Against Power Supply Noise. | Yukiya Miura, Miyuki Inoue, Yuya Kinoshita |
| 2017 | IOLTS | Simulation-based analysis of FF behavior in presence of power supply noise. | Yukiya Miura, Takuya Yamamoto |
| 2015 | ETS | LSI aging estimation using ring oscillators. | Yukiya Miura, Tatsunori Ikeda |
| 2014 | IOLTS | A noise-tolerant master-slave flip-flop. | Yukiya Miura, Yoshihiro Ohkawa |
| 2012 | ETS | On-chip temperature and voltage measurement for field testing. | Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara |
| 2012 | ITC | DART: Dependable VLSI test architecture and its implementation. | Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura |
| 2011 | ETS | Dual Edge Triggered Flip-Flops for Noise Aware Design. | Yukiya Miura |
| 2010 | ETS | On estimation of NBTI-Induced delay degradation. | Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura |
| 2007 | ITC | Dependable clock distribution for crosstalk aware design. | Yukiya Miura |
| 2001 | ETS | Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. | Yukiya Miura, Shuichi Seno |
| 1997 | ITC | An IDDQ Sensor Circuit for Low-Voltage ICs. | Yukiya Miura |
| 1995 | ITC | A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. | Yukiya Miura |
| 1994 | ISCAS | A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. | Yukiya Miura, Sachio Naito, Kozo Kinoshita |
| 1992 | ITC | Circuit Design for Built-in Current Testing. | Yukiya Miura, Kozo Kinoshita |