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Zaid Al-Ars

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

59

Venues

22

Active years

2000–2025

Best venue rank

A*

Where they publish

Papers

59 indexed papers, newest first.

YearVenueTitleAuthors
2025IJCNNSENMap: Multi-objective dataflow mapping & synthesis for hybrid scalable neuromorphic systems.Prithvish Nembhani, Oliver Rhodes, Guangzhi Tang, Alexandra F. Dobrita, Yingfu Xu, Kanishkan Vadivel, Kevin Shidqi, Paul Detterer, Mario Konijnenburg, Gert-Jan van Schaik, Manolis Sifalakis, Zaid Al-Ars, Amirreza Yousefzadeh
2025VLDBHigh Throughput GPU-Accelerated FSST String Compression.Tim Anema, Joost Hoozemans, Zaid Al-Ars, H. Peter Hofstee
2024IJCNNSENSIM: An Event-driven Parallel Simulator for Multi-core Neuromorphic Systems.Prithvish Nembhani, Kanishkan Vadivel, Guangzhi Tang, Mohammad Tahghighi, Gert-Jan van Schaik, Manolis Sifalakis, Zaid Al-Ars, Amirreza Yousefzadeh
2024QCEAssessing the Requirements for Industry Relevant Quantum Computation.Anna M. Krol, Marvin Erdmann, Ewan Munro, Andr Luckow, Zaid Al-Ars
2023BIBENLICE: Synthetic Medical Record Generation for Effective Primary Healthcare Differential Diagnosis.Zaid Al-Ars, Obinna Agba, Zhuoran Guo, Christiaan Boerkamp, Ziyaad Jaber, Tareq Jaber
2023QCEEfficient Parameterised Compilation for Hybrid Quantum Programming.Anna M. Krol, Koen Mesman, Aritra Sarkar, Zaid Al-Ars
2023SCOctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications.Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, H. Peter Hofstee
2023SCTydi-lang: A Language for Typed Streaming Hardware.Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
2023VLDBAn Intermediate Representation for Composable Typed Streaming Dataflow Designs.Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten
2022BMVCImproving Gradient Paths for Binary Convolutional Neural Networks.Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
2022ISPDCCommunication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight.Tanveer Ahmad, Chengxin Ma, Zaid Al-Ars, H. Peter Hofstee
2021ICANNAn Attention Module for Convolutional Neural Networks.Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars
2021IJCAIAutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression.Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars
2020DSDDesign and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project.Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jir Kadlec, Pekka Jskelinen, Marcos Martinez de Alejandro, Jukka Saarinen, Tero Sntti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer
2020ECAITowards Lossless Binary Convolutional Neural Networks Using Piecewise Approximation.Baozhou Zhu, Zaid Al-Ars, Wei Pan
2020FPGASynthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations.Rene Miedema, Georgios Smaragdos, Mario Negrello, Zaid Al-Ars, Matthias Mller, Christos Strydis
2020IJCNNNASB: Neural Architecture Search for Binary Convolutional Neural Networks.Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee
2020PDPParallelization of Variable Rate Decompression through Metadata.Lennart Noordsij, Steven van der Vlugt, Mohamed A. Bamakhrama, Zaid Al-Ars, Peter Lindstrom
2019FCCMA Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model.Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
2019FPLFletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow.Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee
2018BIBEComparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM.Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars
2018BIBEAn Efficient GPU-Based de Bruijn Graph Construction Algorithm for Micro-Assembly.Shanshan Ren, Nauman Ahmed, Koen Bertels, Zaid Al-Ars
2018DATEIndustrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling.Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars
2018DATEAn industrial case study of low cost adaptive voltage scaling using delay test patterns.Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars
2017BIBEPredictive Genome Analysis Using Partial DNA Sequencing Data.Nauman Ahmed, Koen Bertels, Zaid Al-Ars
2017BIBEHigh Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL.Ernst Houtgast, Vlad Mihai Sima, Zaid Al-Ars
2017BIBEStreaming Distributed DNA Sequence Alignment Using Apache Spark.Hamid Mushtaq, Nauman Ahmed, Zaid Al-Ars
2017BIBEGPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization.Shanshan Ren, Koen Bertels, Zaid Al-Ars
2016DATEChallenges of using on-chip performance monitors for process and environmental variation compensation.Mahroo Zandrahimi, Zaid Al-Ars, Philippe Debaud, Armand Castillejo
2016FCCMPower-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms.Ernst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars
2015DATEAccelerating complex brain-model simulations on GPU platforms.Hoang Anh Du Nguyen, Zaid Al-Ars, Georgios Smaragdos, Christos Strydis
2015ICCADHeterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm.Nauman Ahmed, Vlad Mihai Sima, Ernst Houtgast, Koen Bertels, Zaid Al-Ars
2013DATEEfficient software-based fault tolerance approach on multicore platforms.Hamid Mushtaq, Zaid Al-Ars, Koen Bertels
2013DATEHybrid interconnect design for heterogeneous hardware accelerators.Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jrgen Becker, Koen Bertels
2012DDECSA user-level library for fault tolerance on shared memory multicore systems.Hamid Mushtaq, Zaid Al-Ars, Koen Bertels
2012SCDetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems.Hamid Mushtaq, Zaid Al-Ars, Koen Bertels
2011DDECSInfluence of parasitic memory effect on single-cell faults in SRAMs.Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell
2011ETSMemory Test Optimization for Parasitic Bit Line Coupling in SRAMs.Sandra Irobi, Zaid Al-Ars, Said Hamdioui
2010ITCDetecting memory faults in the presence of bit line coupling in SRAM devices.Sandra Irobi, Zaid Al-Ars, Said Hamdioui
2010VTSBit line coupling memory tests for single-cell fails in SRAMs.Sandra Irobi, Zaid Al-Ars, Said Hamdioui
2010SAFECOMPINDEXYS, a Logical Step beyond GENESYS.Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, Gyrgy Csertn, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler
2008DSDAcceleration of Smith-Waterman using Recursive Variable Expansion.Zubair Nawaz, Zaid Al-Ars, Koen Bertels, Mudassir Shabbir
2008ITCDefect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller
2007DDECSManifestation of Precharge Faults in High Speed DRAM Devices.Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
2007ETSPPM Reduction on Embedded Memories in System on Chip.Said Hamdioui, Zaid Al-Ars, Javier Jimnez, Jose Calero
2007VTSOptimizing Test Length for Soft Faults in DRAM Devices.Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
2006DATESpace of DRAM fault models and corresponding testing.Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor
2006ITCDRAM-Specific Space of Memory Tests.Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jrg E. Vollrath
2005DATEFramework for Fault Analysis and Test Generation in DRAMs.Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor
2004DATESoft Faults and the Importance of Stresses in Memory Testing.Zaid Al-Ars, Ad J. van de Goor
2004ETSTests for address decoder delay faults in RAMs due to inter-gate opens.Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars
2004VTSEffects of Bit Line Coupling on the Faulty Behavior of DRAMs.Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor
2003DATEOptimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation.Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter
2002DATEModeling Techniques and Tests for Partial Faults in Memory Devices.Zaid Al-Ars, Ad J. van de Goor
2002VTSApproximating Infinite Dynamic Behavior for DRAM Cell Defects.Zaid Al-Ars, Ad J. van de Goor
2002VTSTesting Static and Dynamic Faults in Random Access Memories.Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor
2001DATEStatic and dynamic behavior of memory cell array opens and shorts in embedded DRAMs.Zaid Al-Ars, Ad J. van de Goor
2001ITCSimulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter
2000VTSFunctional Memory Faults: A Formal Notation and a Taxonomy.Ad J. van de Goor, Zaid Al-Ars