| 2025 | GECCO | TinyverseGP: Towards a Modular Cross-domain Benchmarking Framework for Genetic Programming. | Roman Kalkreuth, Fabrcio Olivetti de Frana, Anja Jankovic, Marie Anastacio, Julian Dierkes, Zdenek Vascek, Holger H. Hoos |
| 2025 | GECCO | Towards Efficient Semantic Mutation in CGP: Enhancing SOMO | Lukas Plevac, Zdenek Vascek |
| 2025 | GECCO | Efficient Scheduling of Transformer Neural Network Computation for Edge-AI Deployment. | David Sedlak, Jan Klhufek, Vojtech Mrazek, Zdenek Vascek |
| 2025 | ISCAS | AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. | Vojtech Mrazek, Zdenek Vascek |
| 2024 | CEC | Automated Synthesis of Commutative Approximate Arithmetic Operators. | Zdenek Vascek |
| 2024 | DATE | Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2024 | DDECS | Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. | Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2024 | ICCAD | Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. | Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vascek, Kostas Siozios, Georgios Tzimpragos, Mehdi B. Tahoori, Georgios Zervakis |
| 2023 | FOGA | General Boolean Function Benchmark Suite. | Roman Kalkreuth, Zdenek Vascek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bck |
| 2023 | GECCO | Towards a General Boolean Function Benchmark Suite. | Roman Kalkreuth, Zdenek Vascek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bck |
| 2023 | ICCAD | Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. | Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2022 | GECCO | Graph-based genetic programming. | Roman Kalkreuth, Lo Franoso Dal Piccol Sotto, Zdenek Vascek |
| 2021 | DDECS | Synthesis of approximate circuits for LUT-based FPGAs. | Zdenek Vascek |
| 2021 | DSD | Resynthesis of logic circuits using machine learning and reconvergent paths. | Jitka Kocnov, Zdenek Vascek |
| 2020 | DAC | ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. | Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2020 | DATE | TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. | Filip Vaverka, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2020 | ETS | Design, Verification, Test and In-Field Implications of Approximate Computing Systems. | Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Snchez, Alessandro Savino, Luks Sekanina, Marcello Traiola, Zdenek Vascek, Arnaud Virazel |
| 2020 | GECCO | Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. | David Hodan, Vojtech Mrazek, Zdenek Vascek |
| 2019 | DAC | autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. | Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2019 | DATE | Automated Circuit Approximation Method Driven by Data Distribution. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2019 | EUROGP | Towards a Scalable EA-Based Optimization of Digital Circuits. | Jitka Kocnov, Zdenek Vascek |
| 2019 | GECCO | Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. | Jitka Kocnov, Zdenek Vascek |
| 2019 | ICCAD | ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. | Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique |
| 2019 | ISCAS | EA-Based Refactoring of Mapped Logic Circuits. | Jitka Kocnov, Zdenek Vascek |
| 2018 | CAV | ADAC: Automated Design of Approximate Circuits. | Milan Ceska, Jir Matys, Vojtech Mrazek, Luks Sekanina, Zdenek Vascek, Toms Vojnar |
| 2018 | GECCO | Evolving boolean functions for fast and efficient randomness testing. | Vojtech Mrazek, Marek Ss, Zdenek Vascek, Luks Sekanina, Vashek Matyas |
| 2018 | GECCO | Evolutionary design of large approximate adders optimized for various error criteria. | Vojtech Mrazek, Zdenek Vascek |
| 2018 | VTS | Special session: How approximate computing impacts verification, test and reliability. | Luks Sekanina, Zdenek Vascek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo |
| 2017 | DATE | EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. | Vojtech Mrazek, Radek Hrbacek, Zdenek Vascek, Luks Sekanina |
| 2017 | DATE | Towards low power approximate DCT architecture for HEVC standard. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2017 | GECCO | Parallel optimization of transistor level circuits using cartesian genetic programming. | Vojtech Mrazek, Zdenek Vascek |
| 2017 | ICCAD | Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. | Milan Ceska, Jir Matys, Vojtech Mrazek, Luks Sekanina, Zdenek Vascek, Toms Vojnar |
| 2016 | FPL | Search-based synthesis of approximate circuits implemented into FPGAs. | Zdenek Vascek, Luks Sekanina |
| 2016 | ICCAD | Design of power-efficient approximate multipliers for approximate artificial neural networks. | Vojtech Mrazek, Syed Shakib Sarwar, Luks Sekanina, Zdenek Vascek, Kaushik Roy |
| 2015 | EUC | Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. | Vojtech Mrazek, Zdenek Vascek |
| 2015 | EUROGP | Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. | Vojtech Mrazek, Zdenek Vascek |
| 2015 | EUROGP | Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. | Zdenek Vascek |
| 2015 | EUROGP | Circuit Approximation Using Single- and Multi-objective Cartesian GP. | Zdenek Vascek, Luks Sekanina |
| 2015 | GECCO | Evolutionary Approximation of Software for Embedded Systems: Median Function. | Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2015 | GECCO | Evolutionary Approximation of Complex Digital Circuits. | Zdenek Vascek, Luks Sekanina |
| 2014 | CEC | Cartesian genetic programming as local optimizer of logic networks. | Luks Sekanina, Ondrej Ptak, Zdenek Vascek |
| 2014 | DDECS | Evolutionary design of approximate multipliers under different error metrics. | Zdenek Vascek, Luks Sekanina |
| 2014 | EUROGP | On Evolution of Multi-category Pattern Classifiers Suitable for Embedded Systems. | Zdenek Vascek, Michal Bidlo |
| 2013 | CEC | Evolution of cellular automata with conditionally matching rules. | Michal Bidlo, Zdenek Vascek |
| 2012 | CEC | Evolution of cellular automata using instruction-based approach. | Michal Bidlo, Zdenek Vascek |
| 2012 | CEC | Two-step evolution of polymorphic circuits for image multi-filtering. | Luks Sekanina, Vojtech Salajka, Zdenek Vascek |
| 2012 | CEC | On area minimization of complex combinational circuits using cartesian genetic programming. | Zdenek Vascek, Luks Sekanina |
| 2012 | DATE | A SAT-based fitness function for evolutionary optimization of polymorphic circuits. | Luks Sekanina, Zdenek Vascek |
| 2012 | EUROGP | Efficient Phenotype Evaluation in Cartesian Genetic Programming. | Zdenek Vascek, Karel Slan |
| 2011 | CEC | Evolutionary design of robust noise-specific image filters. | Zdenek Vascek, Michal Bidlo |
| 2011 | DATE | A global postsynthesis optimization method for combinational circuits. | Zdenek Vascek, Luks Sekanina |
| 2010 | DATE | A method for design of impulse bursts noise filters optimized for FPGA implementations. | Zdenek Vascek, Luks Sekanina, Michal Bidlo |
| 2010 | DDECS | On logic synthesis of conventionally hard to synthesize circuits using genetic programming. | Petr Fiser, Jan Schmidt, Zdenek Vascek, Luks Sekanina |
| 2009 | CEC | Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model. | Michal Bidlo, Zdenek Vascek |
| 2009 | GECCO | Development of combinational circuits using non-uniform cellular automata: initial results. | Michal Bidlo, Zdenek Vascek |
| 2008 | DDECS | Novel Hardware Implementation of Adaptive Median Filters. | Zdenek Vascek, Luks Sekanina |
| 2008 | EUROGP | Hardware Accelerators for Cartesian Genetic Programming. | Zdenek Vascek, Luks Sekanina |
| 2007 | FPL | An area-efficient alternative to adaptive median filtering in FPGAs. | Zdenek Vascek, Luks Sekanina |