Zhenghong Jiang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2014–2019
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | DAC | Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. | Zhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang |
| 2018 | ICCAD | High-level synthesis with timing-sensitive information flow enforcement. | Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang |
| 2017 | FPGA | NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. | Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang |
| 2015 | FPL | A technology mapper for depth-constrained FPGA logic cells. | Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne |
| 2014 | FPL | Exploring architecture parameters for dual-output LUT based FPGAs. | Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang |