| 2010 | A performance-constrained template-based layout retargeting algorithm for analog integrated circuits. | Zheng Liu, Lihong Zhang |
| 2010 | Simultaneous slack budgeting and retiming for synchronous circuits optimization. | Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang |
| 2010 | Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks. | Tiantian Liu, Minming Li, Chun Jason Xue |
| 2010 | Minimizing clock latency range in robust clock tree synthesis. | Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen |
| 2010 | D-A converter based variation analysis for analog layout design. | Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake |
| 2010 | Efficient power grid integrity analysis using on-the-fly error check and reduction. | Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai |
| 2010 | Source-level timing annotation for fast and accurate TLM computation model generation. | Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay |
| 2010 | Dead via minimization by simultaneous routing and redundant via insertion. | Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li |
| 2010 | CAD reference flow for 3D via-last integrated circuits. | Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu |
| 2010 | UFO: unified convex optimization algorithms for fixed-outline floorplanning. | Jai-Ming Lin, Hsi Hung |
| 2010 | Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. | Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang Huang |
| 2010 | PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. | Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong |
| 2010 | MPSoC programming using the MAPS compiler. | Rainer Leupers, Jernimo Castrilln |
| 2010 | VISA: versatile impulse structure approximation for time-domain linear macromodeling. | Chi-Un Lei, Ngai Wong |
| 2010 | Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors. | Jungseob Lee, Shi-Ting Zhou, Nam Sung Kim |
| 2010 | A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance. | Yu-Min Lee, Tsung-You Wu, Po-Yi Chiang |
| 2010 | Technique for controlling power-mode transition noise in distributed sleep transistor network. | Yongho Lee, Taewhan Kim |
| 2010 | Fault-tolerant resynthesis with dual-output LUTs. | Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li |
| 2010 | Dynamic voltage domain assignment technique for low power performance manageable cell based design. | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2010 | Incremental high-level synthesis. | Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama |
| 2010 | Formal verification of tunnel diode oscillator with temperature variations. | Kusum Lata, H. S. Jamadagni |
| 2010 | Homogeneous integration for 3D IC with TSV. | Ding-Ming Kwai |
| 2010 | Design and verification methods of Toshiba's wireless LAN baseband SoC. | Masanori Kuwahara |
| 2010 | Optimal simultaneous pin assignment and escape routing for dense PCBs. | Hui Kong, Tan Yan, Martin D. F. Wong |
| 2010 | CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles. | Yukihide Kohira, Atsushi Takahashi |