| 2010 | A CMOS image sensor with 2.0-e | Takahiro Kohara, Woonghee Lee, Koichi Mizobuchi, Shigetoshi Sugawa |
| 2010 | An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation. | Jungsoo Kim, Younghoon Lee, Sungjoo Yoo, Chong-Min Kyung |
| 2010 | A global interconnect reduction technique during high level synthesis. | Taemin Kim, Xun Liu |
| 2010 | Low-cost design for repair with circuit partitioning. | Kyungho Kim, Byungtae Kang, Donghyun Kim, Sungchul Lee, Juyong Shin, Hyunchul Shin |
| 2010 | Clock tree embedding for 3D ICs. | Tak-Yung Kim, Taewhan Kim |
| 2010 | Checkered white-RGB color LOFIC CMOS image sensor. | Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa |
| 2010 | Improved on-chip router analytical power and area modeling. | Andrew B. Kahng, Bill Lin, Kambiz Samadi |
| 2010 | Slack redistribution for graceful degradation under voltage overscaling. | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
| 2010 | Analyzing electrical effects of RTA-driven local anneal temperature variation. | Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
| 2010 | An alternative polychronous model and synthesis methodology for model-driven embedded software. | Bijoy Antony Jose, Sandeep K. Shukla |
| 2010 | A3MAP: architecture-aware analytic mapping for networks-on-chip. | Wooyoung Jang, David Z. Pan |
| 2010 | A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. | Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa |
| 2010 | Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. | Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo |
| 2010 | An adaptive parallel flow for power distribution network simulation using discrete Fourier transform. | Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng |
| 2010 | Trace-based performance analysis framework for heterogeneous multicore systems. | Shih-Hao Hung, Chia-Heng Tu, Thean-Siew Soon |
| 2010 | Adaptive power management for real-time event streams. | Kai Huang, Luca Santinelli, Jian-Jia Chen, Lothar Thiele, Giorgio C. Buttazzo |
| 2010 | Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. | Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan |
| 2010 | PAC duo system power estimation at ESL. | Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang |
| 2010 | TRECO: dynamic technology remapping for timing engineering change orders. | Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang |
| 2010 | Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts. | Rui He, Lihong Zhang |
| 2010 | Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory. | Yi He, Chun Jason Xue, Cathy Qun Xu, Edwin Hsing-Mean Sha |
| 2010 | Graph partition based path selection for testing of small delay defects. | Zijian He, Tao Lv, Huawei Li, Xiaowei Li |
| 2010 | A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources. | Zhigang Hao, Guoyong Shi |
| 2010 | SOC for car navigation system with a 55.3GOPS image recognition engine. | Hiroyuki Hamasaki, Yasuhiko Hoshi, Atsushi Nakamura, Akihiro Yamamoto, Hideaki Kido, Shoji Muramatsu |
| 2010 | Manifold construction and parameterization for nonlinear manifold-based model reduction. | Chenjie Gu, Jaijeet S. Roychowdhury |