| 2010 | Current source modeling in the presence of body bias. | Saket Gupta, Sachin S. Sapatnekar |
| 2010 | Platform modeling for exploration and synthesis. | Andreas Gerstlauer, Gunar Schirner |
| 2010 | Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2010 | Design and chip implementation of an instruction scheduling free ubiquitous processor. | Masa-Aki Fukase, Ryosuke Murakami, Tomoaki Sato |
| 2010 | Secure and testable scan design using extended de Bruijn graphs. | Hideo Fujiwara, Marie Engelene J. Obien |
| 2010 | Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs. | Fabrizio Ferrandi, Christian Pilato, Donatella Sciuto, Antonino Tumeo |
| 2010 | Technology mapping with crosstalk noise avoidance. | Fang-Yu Fan, Hung-Ming Chen, I-Min Liu |
| 2010 | Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. | Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang |
| 2010 | A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. | Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi |
| 2010 | Computer-aided recoding for multi-core systems. | Rainer Dmer |
| 2010 | Dynamic power estimation for deep submicron circuits with process variation. | Quang Dinh, Deming Chen, Martin D. F. Wong |
| 2010 | Efficient throughput-guarantees for latency-sensitive networks-on-chip. | Jonas Diemer, Rolf Ernst, Michael Kauschke |
| 2010 | iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. | Debasish Das, Jia Wang, Hai Zhou |
| 2010 | High level event driven thermal estimation for thermal aware task allocation and scheduling. | Jin Cui, Douglas L. Maskell |
| 2010 | A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection. | Ji Hwan (Paul) Chun, Jae Wook Lee, Jacob A. Abraham |
| 2010 | Built-in self at-speed delay binning and calibration mechanism in wireless test platform. | Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng |
| 2010 | Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. | Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng |
| 2010 | Optimizing blocks in an SoC using symbolic code-statement reachability analysis. | Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo |
| 2010 | Improved clock-gating control scheme for transparent pipeline. | Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy |
| 2010 | An industrial perspective of 3D IC integration technology: from the viewpoint of design technology. | Kyu-Myung Choi |
| 2010 | Correlating system test Fmax with structural test Fmax and process monitoring measurements. | Janine Chen, Jing Zeng, Li-C. Wang, Michael Mateja |
| 2010 | Parametric yield driven resource binding in behavioral synthesis with multi- | Yibo Chen, Yuan Xie, Yu Wang, Andrs Takach |
| 2010 | Minimizing leakage power in aging-bounded high-level synthesis with design time multi- | Yibo Chen, Yuan Xie, Yu Wang, Andrs Takach |
| 2010 | An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development. | Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang |
| 2010 | On confidence in characterization and application of variation models. | Lerong Cheng, Puneet Gupta, Lei He |