| 2008 | Timing-power optimization for mixed-radix Ling adders by integer linear programming. | Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng |
| 2008 | A delay model for interconnect trees based on ABCD matrix. | Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng |
| 2008 | Reconfigurable RTD-based circuit elements of complete logic functionality. | Yexin Zheng, Chao Huang |
| 2008 | Symmetry-aware placement with transitive closure graphs for analog layout design. | Lihong Zhang, Chuanjin Richard Shi, Yingtao Jiang |
| 2008 | High performance current-mode differential logic. | Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto |
| 2008 | Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. | Sushu Zhang, Karam S. Chatha |
| 2008 | Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. | Heng Yu, Bharadwaj Veeravalli, Yajun Ha |
| 2008 | Automatic interface synthesis based on the classification of interface protocols of IPs. | ChangRyul Yun, DongSoo Kang, YoungHwan Bae, Hanhn Cho, KyoungSon Jhang |
| 2008 | SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. | Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek |
| 2008 | Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees. | Shan Yan, Bill Lin |
| 2008 | Faster projection based methods for circuit level verification. | Chao Yan, Mark R. Greenstreet |
| 2008 | Floating-point reconfiguration array processor for 3D graphics physics engine. | Hoonmo Yang |
| 2008 | Soft error rate reduction using redundancy addition and removal. | Kai-Chiang Wu, Diana Marculescu |
| 2008 | Load scheduling: Reducing pressure on distributed register files for free. | Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang |
| 2008 | Low power clock buffer planning methodology in F-D placement for large scale circuit design. | Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian |
| 2008 | Variability-driven module selection with joint design time optimization and post-silicon tuning. | Feng Wang, Xiaoxia Wu, Yuan Xie |
| 2008 | Heuristic power/ground network and floorplan co-design method. | Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong |
| 2008 | Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization. | Dawei Wang, Sikun Li, Yong Dou |
| 2008 | A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. | Fei Wang, Yu Hu, Huawei Li, Xiaowei Li |
| 2008 | A fast incremental clock skew scheduling algorithm for slack optimization. | Kui Wang, Hao Fang, Hu Xu, Xu Cheng |
| 2008 | Fast, quasi-optimal, and pipelined instruction-set extensions. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | Predictive models and CAD methodology for pattern dependent variability. | Nishath Verghese, Richard Rouse, Philippe Hurat |
| 2008 | Handling partial correlations in yield prediction. | Sridhar Varadan, Janet Meiling Wang, Jiang Hu |
| 2008 | Parallel fault backtracing for calculation of fault coverage. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2008 | The future of semiconductor industry - A foundry's perspective. | F. C. Tseng |