| 2007 | Frequency Selective Model Order Reduction via Spectral Zero Projection. | Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud |
| 2007 | Systematic Scan Reconfiguration. | Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda |
| 2007 | Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects. | Charbel J. Akl, Magdy A. Bayoumi |
| 2007 | VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond. | Imran Ahmed, Tughrul Arslan |
| 2007 | Fast Analytic Placement using Minimum Cost Flow. | Ameya R. Agnihotri, Patrick H. Madden |
| 2007 | Delay Uncertainty Reduction by Interconnect and Gate Splitting. | Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang |
| 2006 | An unconditional stable general operator splitting method for transistor level transient analysis. | Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh |
| 2006 | Memory size computation for multimedia processing applications. | Hongwei Zhu, Ilie I. Luican, Florin Balasa |
| 2006 | Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton |
| 2006 | A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. | Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi |
| 2006 | Temperature-aware routing in 3D ICs. | Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar |
| 2006 | An efficient algorithm for 3-D reluctance extraction considering high frequency effect. | Mengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang |
| 2006 | Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. | Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen |
| 2006 | Electrothermal analysis and optimization techniques for nanoscale integrated circuits. | Yong Zhan, Brent Goplen, Sachin S. Sapatnekar |
| 2006 | A fixed-die floorplanning algorithm using an analytical approach. | Yong Zhan, Yan Feng, Sachin S. Sapatnekar |
| 2006 | Worst case execution time analysis for synthesized hardware. | Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi |
| 2006 | Parasitics extraction involving 3-D conductors based on multi-layered Green's function. | Zuochang Ye, Zhiping Yu |
| 2006 | Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method. | Changhao Yan, Wenjian Yu, Zeyi Wang |
| 2006 | Adaptive admittance-based conductor meshing for interconnect analysis. | Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan |
| 2006 | Efficient identification of multi-cycle false path. | Kai Yang, Kwang-Ting Cheng |
| 2006 | A transduction-based framework to synthesize RSFQ circuits. | Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi |
| 2006 | Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. | Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jrgen Mattausch |
| 2006 | An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits. | Kiyotaka Yamamura, Wataru Kuroki |
| 2006 | Statistical corner conditions of interconnect delay (corner LPE specifications). | Kenta Yamada, Noriaki Oda |
| 2006 | Transition-based coverage estimation for symbolic model checking. | Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya |