| 2007 | An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. | Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim |
| 2007 | A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. | Yazhuo Dong, Yong Dou |
| 2007 | Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets. | Stefan Disch, Christoph Scholl |
| 2007 | Architectural Optimizations for Text to Speech Synthesis in Embedded Systems. | Soumyajit Dey, Monu Kedia, Anupam Basu |
| 2007 | Coupling-aware Dummy Metal Insertion for Lithography. | Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang |
| 2007 | Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. | S. Dabas, Ning Dong, Jaijeet S. Roychowdhury |
| 2007 | Thermal-Aware 3D IC Placement Via Transformation. | Jason Cong, Guojie Luo, Jie Wei, Yan Zhang |
| 2007 | Synthesis of Reversible Sequential Elements. | Min-Lun Chuang, Chun-Yao Wang |
| 2007 | System Architecture for Software Peripherals. | Siddharth Choudhuri, Tony Givargis |
| 2007 | New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. | Ruiming Chen, Hai Zhou |
| 2007 | Fast Buffer Insertion for Yield Optimization Under Process Variations. | Ruiming Chen, Hai Zhou |
| 2007 | Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems. | Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sheng Shih |
| 2007 | Flow Time Minimization under Energy Constraints. | Jian-Jia Chen, Kazuo Iwama, Tei-Wei Kuo, Hsueh-I Lu |
| 2007 | DFM/DFY practices during physical designs for timing, signal integrity, and power. | Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai |
| 2007 | High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. | Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang |
| 2007 | PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool. | Michael Chan, Adam Postula, Yong Ding |
| 2007 | Fixing Design Errors with Counterexamples and Resynthesis. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2007 | Safe Delay Optimization for Physical Synthesis. | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2007 | Creating Explicit Communication in SoC Models Using Interactive Re-Coding. | Pramod Chandraiah, Junyu Peng, Rainer Dmer |
| 2007 | DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. | Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong |
| 2007 | Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. | Marc Boule, Zeljko Zilic |
| 2007 | Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
| 2007 | Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. | Subhasis Banerjee, G. Surendra, S. K. Nandy |
| 2007 | AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. | Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar |
| 2007 | Deeper Bound in BMC by Combining Constant Propagation and Abstraction. | Roy Armoni, Limor Fix, Ranan Fraer, Tamir Heyman, Moshe Y. Vardi, Yakir Vizel, Yael Zbar |