| 2006 | Constraint driven I/O planning and placement for chip-package co-design. | Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He |
| 2006 | A high-performance platform-based SoC for information security. | Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan |
| 2006 | Delay variation tolerance for domino circuits. | Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang |
| 2006 | Improving routing efficiency for network-on-chip through contention-aware input selection. | Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz |
| 2006 | SAT-based optimal hypergraph partitioning with replication. | Michael G. Wrighton, Andr DeHon |
| 2006 | Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. | Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai |
| 2006 | An SPU reference model for simulation, random test generation and verification. | Yukio Watanabe, Balazs Sallay, Brad W. Michael, Daniel A. Brokenshire, Gavin Meil, Hazim Shafi, Daisuke Hiraoka |
| 2006 | A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. | Minoru Watanabe, Fuminori Kobayashi |
| 2006 | A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles. | Xiren Wang, Wenjian Yu, Zeyi Wang |
| 2006 | Optimization of circuit trajectories: an auxiliary network approach. | Baohua Wang, Pinaki Mazumder |
| 2006 | An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. | Xiaoying Wang, Lars Hedrich |
| 2006 | Optimal TDMA time slot and cycle length allocation for hard real-time systems. | Ernesto Wandeler, Lothar Thiele |
| 2006 | Depth-driven verification of simultaneous interfaces. | Ilya Wagner, Valeria Bertacco, Todd M. Austin |
| 2006 | Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. | Sebastian Vogel, Martin D. F. Wong |
| 2006 | FastPlace 2.0: an efficient analytical placer for mixed-mode designs. | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
| 2006 | Co-synthesis of a configurable SoC platform based on a network on chip architecture. | Mrio P. Vstias, Horcio C. Neto |
| 2006 | Reducing dynamic compilation overhead by overlapping compilation and execution. | Priya Unnikrishnan, Mahmut T. Kandemir, Feihui Li |
| 2006 | Ultra-low voltage power management circuit and computation methodology for energy harvesting applications. | Chi-Ying Tsui, Hui Shao, Wing-Hung Ki, Feng Su |
| 2006 | Interconnect RL extraction at a single representative frequency. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2006 | Monotonic parallel and orthogonal routing for single-layer ball grid array packages. | Yoichi Tomioka, Atsushi Takahashi |
| 2006 | Workload prediction and dynamic voltage scaling for MPEG decoding. | Ying Tan, Parth Malani, Qinru Qiu, Qing Wu |
| 2006 | Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. | Jess Tabero, Julio Septin, Hortensia Mecha, Daniel Mozos |
| 2006 | High level equivalence symmetric input identification. | Ming-Hong Su, Chun-Yao Wang |
| 2006 | FSM-based transaction-level functional coverage for interface compliance verification. | Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou |
| 2006 | Energy savings through embedded processing on disk system. | Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, Feihui Li |