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Asia and South Pacific Design Automation Conference

ASPDAC

B

CORE rank

CORE rank (raw)

B

Fields of research

Distributed Computing and Systems Software

Papers indexed

4,548

1995–2026

Papers per year

1995301 peak2026

ASPDAC papers

4,548 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2006Crosstalk analysis using reconvergence correlation.Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma
2006FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006Wire sizing with scattering effect for nanoscale interconnection.Sean X. Shi, David Z. Pan
2006CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong
2006A near optimal deblocking filter for H.264 advanced video coding.Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
2006Efficient early stage resonance estimation techniques for C4 package.Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
2006A 16-bit, low-power microsystem with monolithic MEMS-Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown
2006Automotive electronics: steady growth for years to come!Alberto L. Sangiovanni-Vincentelli
2006Low area pipelined circuits by multi-clock cycle paths and clock scheduling.Bakhtiar Affendi Rosdi, Atsushi Takahashi
2006Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system.Peng Rong, Massoud Pedram
2006Double edge triggered Feedback Flip-Flop in sub 100NM technology.S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha
2006Robust analytical gate delay modeling for low voltage circuits.Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
2006Hardware implementation of super minimum all digital FM demodulator.Nursani Rahmatullah, Arif E. Nugroho
2006An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model.Yu Pu, Yajun Ha
2006POSIX modeling in SystemC.Hector Posadas, Jess damez, Pablo Snchez, Eugenio Villar, Francisco Blasco
2006Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
2006Simultaneous block and I/O buffer floorplanning for flip-chip design.Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang
2006Constraint-driven bus matrix synthesis for MPSoC.Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
2006Reusable component IP design using refinement-based design environment.Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
2006Utility of the OpenAccess database in academic research.David A. Papa, Igor L. Markov, Philip Chong
2006Abridged addressing: a low power memory addressing strategy.Preeti Ranjan Panda
2006Generation of shorter sequences for high resolution error diagnosis using sequential SAT.Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
2006Optimal topology exploration for application-specific 3D architectures.Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie
2006Compiler-Guided data compression for reducing memory consumption of embedded applications.Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu
2006A 52mW 1200MIPS compact DSP for multi-core media SoC.Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
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