| 2005 | Design and test of a scalable security processor. | Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | Design of clocked circuits using UML. | Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh Kumar Pilakkat |
| 2005 | A generalized quadrature bandpass sampling in radio receivers. | Yi-Ran Sun, Svante Signell |
| 2005 | A configurable AES processor for enhanced security. | Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu |
| 2005 | A practical cut-based physical retiming algorithm for field programmable gate arrays. | Peter Suaris, Dongsheng Wang, Nan-Chi Chou |
| 2005 | Online hardware/software partitioning in networked embedded systems. | Thilo Streichert, Christian Haubelt, Jrgen Teich |
| 2005 | Leakage control in FPGA routing fabric. | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan |
| 2005 | SAGA: synthesis technique for guaranteed throughput NoC architectures. | Krishnan Srinivasan, Karam S. Chatha |
| 2005 | AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. | Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis |
| 2005 | Yield driven gate sizing for coupling-noise reduction under uncertainty. | Debjit Sinha, Hai Zhou |
| 2005 | A Huffman-based coding with efficient test application. | Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue |
| 2005 | Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18m CMOS process. | Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera |
| 2005 | Optimizing intra-task voltage scheduling using data flow analysis. | Dongkun Shin, Jihong Kim |
| 2005 | Reconfigurable adaptive FEC system with interleaving. | Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto |
| 2005 | SPIN-PAC: test compaction for speed-independent circuits. | Feng Shi, Yiorgos Makris |
| 2005 | Bridging fault testability of BDD circuits. | Junhao Shi, Grschwin Fey, Rolf Drechsler |
| 2005 | A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder. | Bo Shen, Junhua Tian, Zheng Li, Jianing Su, Qianling Zhang |
| 2005 | A fast counterexample minimization approach with refutation analysis and incremental SAT. | ShengYu Shen, Ying Qin, Sikun Li |
| 2005 | Priority directed test generation for functional verification using neural networks. | Hao Shen, Yuzhuo Fu |
| 2005 | Synthesis of quantum logic circuits. | Vivek V. Shende, Stephen S. Bullock, Igor L. Markov |
| 2005 | High-level synthesis for DSP applications using heterogeneous functional units. | Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha |
| 2005 | Congestion prediction in floorplanning. | Chiu-Wing Sham, Evangeline F. Y. Young |
| 2005 | A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. | Jaewon Seo, Nikil D. Dutt |
| 2005 | A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. | Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel |
| 2005 | A perturbation-aware noise convergence methodology for high frequency microprocessors. | Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda |