| 2005 | Area-IO DRAM/logic integration with system-in-a-package (SiP). | Anru Wang, Wayne Wei-Ming Dai |
| 2005 | A monolithic CMOS L band DAB receiver. | Ziqiang Wang, Baoyong Chi, Min Lin, Shuguang Han, Lu Liu, Jinke Yao, Zhihua Wang |
| 2005 | K-disjointness paradigm with application to symmetry detection for incompletely specified functions. | Kuo-Hua Wang, Jia-Hung Chen |
| 2005 | Abstracting functionality for modular performance analysis of hard real-time systems. | Ernesto Wandeler, Lothar Thiele |
| 2005 | Designing reliable circuit in the presence of soft errors. | Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin |
| 2005 | An efficient control-oriented coverage metric. | Shireesh Verma, Kiran Ramineni, Ian G. Harris |
| 2005 | Skew scheduling and clock routing for improved tolerance to process variations. | Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu |
| 2005 | Comparison of schemes for encoding unobservability in translation to SAT. | Miroslav N. Velev |
| 2005 | Stability analysis of active clock deskewing systems using a control theoretic approach. | Vinil Varghese, Tom Chen, Peter Michael Young |
| 2005 | Return path selection for loop RL extraction. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2005 | Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. | Jeng-Liang Tsai, Charlie Chung-Ping Chen |
| 2005 | A fractional delay-locked loop for on chip clock generation applications. | Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi |
| 2005 | Forward discrete probability propagation method for device performance characterization under process variations. | Rasit Onur Topaloglu, Alex Orailoglu |
| 2005 | Efficient synthesis of speed-independent combinational logic circuits. | William B. Toms, David A. Edwards |
| 2005 | Event-oriented computing with reconfigurable platform. | Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita |
| 2005 | A processor core synthesis system in IP-based SoC design. | Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2005 | Power minimization for dynamic PLAs. | Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh |
| 2005 | Gibbs sampling in power grid analysis. | Zhixin Tian, Huazhong Yang, Rong Luo |
| 2005 | A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion. | K. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian |
| 2005 | A bipolar IF amplifier/RSSI for ASK receiver. | Yonggang Tao, Yongsheng Xu, Wei Jin, Hui Yu, Zongsheng Lai |
| 2005 | Optimal redistribution of white space for wire length minimization. | Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong |
| 2005 | A novel data processing circuit in high-speed serial communication. | Yongjian Tang, Lenian He, Xiaolang Yan |
| 2005 | Prediction of LC-VCOs' tuning curves with period calculation technique. | Zhangwen Tang, Jie He, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min |
| 2005 | An accurate 1.08-GHz CMOS LC voltage-controlled oscillator. | Zhangwen Tang, Jie He, Hongyan Jian, Hao Min |
| 2005 | Performance driven reliable link design for networks on chips. | Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli |