| 2005 | Using loop invariants to fight soft errors in data caches. | Sri Hari Krishna Narayanan, Seung Woo Son, Mahmut T. Kandemir, Feihui Li |
| 2005 | Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. | Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis |
| 2005 | A variation-aware low-power coding methodology for tightly coupled buses. | Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura |
| 2005 | Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. | Srinivasan Murali, Luca Benini, Giovanni De Micheli |
| 2005 | Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm. | Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi |
| 2005 | Evaluation of dual V | Rajarshi Mukherjee, Seda Ogrenci Memik |
| 2005 | A low-power video segmentation LSI with boundary-active-only architecture. | Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jrgen Mattausch |
| 2005 | Resource sharing in pipelined CDFG synthesis. | Somsubhra Mondal, Seda Ogrenci Memik |
| 2005 | Automatic extraction of function bodies from software binaries. | Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee |
| 2005 | An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system. | Osamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta |
| 2005 | Time and energy efficient mapping of embedded applications onto NoCs. | Csar A. M. Marcon, Andr Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flvio Rech Wagner |
| 2005 | Modern FPGA constrained placement. | Wai-Kei Mak |
| 2005 | Silicon compilation: the answer to reducing IC development costs. | Rajeev Madhavan |
| 2005 | Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms. | Zhe Ma, Francky Catthoor, Johan Vounckx |
| 2005 | Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. | Zhong-Ching Lu, Ting-Chi Wang |
| 2005 | Register placement for low power clock network. | Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
| 2005 | Feasibility analysis of messages for on-chip networks using wormhole routing. | Zhonghai Lu, Axel Jantsch, Ingo Sander |
| 2005 | Reducing leakage power in instruction cache using WDC for embedded processors. | Xin Lu, Yuzhuo Fu |
| 2005 | Improving the scalability of SAMBA bus architecture. | Ruibing Lu, Aiqun Cao, Cheng-Kok Koh |
| 2005 | TED+: a data structure for microprocessor verification. | Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi |
| 2005 | Forward symbolic model checking for real time systems. | Georgios Logothetis |
| 2005 | Automatic functional test program generation for microprocessor verification. | Tun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li |
| 2005 | On-chip accumulated jitter measurement for phase-locked loops. | Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang |
| 2005 | Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. | Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou |
| 2005 | Hierarchical analysis of process variation for mixed-signal systems. | Fang Liu, Sule Ozev |