| 2005 | A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines. | Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay |
| 2005 | Making fast buffer insertion even faster via approximation techniques. | Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
| 2005 | Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. | Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou |
| 2005 | Placement with symmetry constraints for analog layout design using TCG-S. | Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang |
| 2005 | Propagation delay fault: a new fault model to test delay faults. | Xijiang Lin, Janusz Rajski |
| 2005 | Constraint extraction for pseudo-functional scan-based delay testing. | Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng |
| 2005 | Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. | Yan Lin, Fei Li, Lei He |
| 2005 | System-level design space exploration for security processor prototyping in analytical approaches. | Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee |
| 2005 | Design and design automation of rectification logic for engineering change. | Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone |
| 2005 | An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. | Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim |
| 2005 | Oscillation ring based interconnect test scheme for SOC. | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen |
| 2005 | A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding. | Tiejun Li, Sikun Li, Cheng-Dong Shen |
| 2005 | A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18m CMOS technology. | Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao |
| 2005 | Floorplan management: incremental placement for gate sizing and buffer insertion. | Chen Li, Cheng-Kok Koh, Patrick H. Madden |
| 2005 | An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. | Lingfeng Li, Satoshi Goto, Takeshi Ikenaga |
| 2005 | Compact and stable modeling of partial inductance and reluctance matrices. | Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong |
| 2005 | Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. | Jin-Fu Li |
| 2005 | Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. | Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung |
| 2005 | Design of an application-specific PLD architecture. | Jae-Jin Lee, Gi-Yong Song |
| 2005 | A novel O(n) parallel banker's algorithm for System-on-a-Chip. | Jaehwan John Lee, Vincent John Mooney III |
| 2005 | Power estimation starategies for a low-power security processor. | Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang |
| 2005 | Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. | Dongwoo Lee, David T. Blaauw, Dennis Sylvester |
| 2005 | Process variation robust clock tree routing. | Wai-Ching Douglas Lam, Cheng-Kok Koh |
| 2005 | Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. | Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury |
| 2005 | Embedded software generation from system level specification for multi-tasking embedded systems. | KiSeun Kwon, Youngmin Yi, Dohyung Kim, Soonhoi Ha |