| 2005 | Improved Boolean function hashing based on multiple-vertex dominators. | Ren Krenz, Elena Dubrova |
| 2005 | A fast algorithm for finding common multiple-vertex dominators in circuit graphs. | Ren Krenz, Elena Dubrova |
| 2005 | Register-transfer level functional scan for hierarchical designs. | Ho Fai Ko, Qiang Xu, Nicola Nicolici |
| 2005 | A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. | Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera |
| 2005 | A fast digit-serial systolic multiplier for finite field | Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong |
| 2005 | A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. | Minho Kim, Ingu Hwang, Soo-Ik Chae |
| 2005 | Static analysis and automatic code synthesis of flexible FSM model. | Dohyung Kim, Soonhoi Ha |
| 2005 | Clustering techniques for coarse-grained, antifuse FPGAs. | Chang Woo Kang, Massoud Pedram |
| 2005 | Using data replication to reduce communication energy on chip multiprocessors. | Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran |
| 2005 | A flexible framework for communication evaluation in SoC design. | Praveen Kalla, Xiaobo Sharon Hu, Jrg Henkel |
| 2005 | Studying interactions between prefetching and cache line turnoff. | Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen |
| 2005 | A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. | Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He |
| 2005 | Using GALS architecture to reduce the impact of long wire delay on FPGA performance. | Xin Jia, Ranga Vemuri |
| 2005 | Standard | Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao |
| 2005 | An improved test access mechanism structure and optimization technique in system-on-chip. | Jianhua Feng, Jieyi Long, Wenhua Xu, Hongfei Ye |
| 2005 | An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
| 2005 | Comprehensive frequency dependent interconnect extraction and evaluation methodology. | Rong Jiang, Charlie Chung-Ping Chen |
| 2005 | The development of integrated circuit industry in China. | Zhenghua Jiang |
| 2005 | Microarchitecture evaluation with floorplanning and interconnect pipelining. | Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong |
| 2005 | Evaluation of on-chip transmission line interconnect using wire length distribution. | Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu |
| 2005 | PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits. | Chanseok Hwang, Massoud Pedram |
| 2005 | An-OARSMan: obstacle-avoiding routing tree construction with good length performance. | Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan |
| 2005 | Power minimization techniques on distributed real-time systems by global and local slack management. | Shaoxiong Hua, Gang Qu |
| 2005 | A design of high speed double precision floating point adder using macro modules. | Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li |
| 2005 | Sequential equivalence checking using cuts. | Wei Huang, Pushan Tang, Min Ding |