| 2005 | Clock network minimization methodology based on incremental placement. | Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu |
| 2005 | Using fault model relaxation to diagnose real scan chain defects. | Yu Huang, Wu-Tung Cheng, Greg Crowell |
| 2005 | MUP: a minimal unsatisfiability prover. | Jinbo Huang |
| 2005 | Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions. | Anup Hosangadi, Farzan Fallah, Ryan Kastner |
| 2005 | A system-level approach to hardware reconfigurable systems. | Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jrgen Teich |
| 2005 | Enabling RTOS simulation modeling in a system level design language. | M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
| 2005 | Timing analysis considering temporal supply voltage fluctuation. | Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera |
| 2005 | Design of vehicle position tracking system using short message services and its implementation on FPGA. | Arias Tanti Hapsari, Eniman Y. Syamsudin, Imron Pramana |
| 2005 | An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000. | Yanju Han, Chao Xu, Yizhen Zhang |
| 2005 | Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li |
| 2005 | Adiabatic CMOS gate and adiabatic circuit design for low-power applications. | Guoqiang Hang |
| 2005 | The development of high performance FFT IP cores through hybrid low power algorithmic methodology. | Wei Han, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan |
| 2005 | A class D audio power amplifier with high-efficiency and low-distortion. | Hai Chen, Xiaobo Wu |
| 2005 | Detailed placement for improved depth of focus and CD control. | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park |
| 2005 | Challenges to covering the high-level to silicon gap. | Bill Grundmann |
| 2005 | Design of an efficient memory subsystem for network processor. | Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li |
| 2005 | System-level communication modeling for network-on-chip synthesis. | Andreas Gerstlauer, Dongwan Shin, Rainer Dmer, Daniel D. Gajski |
| 2005 | A function generator-based reconfigurable system. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. | Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti |
| 2005 | VLSI on-chip power/ground network optimization considering decap leakage currents. | Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan |
| 2005 | Comprehensive analysis and optimization of CMOS LNA noise performance. | Dong Feng, Bingxue Shi |
| 2005 | Partitioned model checking from software specifications. | Xiushan Feng, Alan J. Hu, Jin Yang |
| 2005 | Logic optimization using rule-based randomized search. | Petra Frm, Elena Dubrova, Andreas Kuehlmann |
| 2005 | Crossbar based design schemes for switch boxes and programmable interconnection networks. | Hongbing Fan, Yu-Liang Wu |
| 2005 | Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity. | G. Peter Fang, David C. Yeh, David T. Zweidinger, Lawrence A. Arledge Jr., Vinod Gupta |