| 2005 | Placement for configurable dataflow architecture. | Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim |
| 2005 | Lower bounds for dynamic BDD reordering. | Rdiger Ebendt, Rolf Drechsler |
| 2005 | Partial reluctance based circuit simulation is efficient and stable. | Yu Du, Wayne Dai |
| 2005 | A new approach for ring oscillator simulation using the harmonic balance method. | Xiaochun Duan, Kartikeya Mayaram |
| 2005 | Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. | Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty |
| 2005 | Low-power domino circuits using NMOS pull-up on off-critical paths. | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
| 2005 | An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. | Mengmeng Ding, Glenn Wolfe, Ranga Vemuri |
| 2005 | Methodology for high level estimation of FPGA power consumption. | Vijay Degalahal, Tim Tuan |
| 2005 | Wake-up protocols for controlling current surges in MTCMOS-based technology. | Azadeh Davoodi, Ankur Srivastava |
| 2005 | Simultaneous floorplanning and resource binding: a probabilistic approach. | Azadeh Davoodi, Ankur Srivastava |
| 2005 | A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. | Van R. Culver, Sunil P. Khatri |
| 2005 | FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. | John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link |
| 2005 | Thermal-driven multilevel routing for 3-D ICs. | Jason Cong, Yan Zhang |
| 2005 | Fast floorplanning by look-ahead enabled recursive bipartitioning. | Jason Cong, Michail Romesis, Joseph R. Shinnerl |
| 2005 | Are we ready for system-level synthesis? | Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe |
| 2005 | Bitwidth-aware scheduling and binding in high-level synthesis. | Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng |
| 2005 | Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization. | Min Chu, David J. Allstot |
| 2005 | An elitist distributed particle swarm algorithm for RF IC optimization. | Min Chu, David J. Allstot |
| 2005 | Scheduler implementation in MP SoC design. | Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya |
| 2005 | Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. | Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen |
| 2005 | An analog front-end IP for 13.56MHz RFID interrogators. | Junghyun Cho, Suk-Byung Chai, Chung-Gi Song, Kyung-Won Min, Shiho Kim |
| 2005 | A bandwidth efficient subsampling-based block matching architecture for motion estimation. | Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang |
| 2005 | Battery-aware instruction generation for embedded processors. | Newton Cheung, Sri Parameswaran, Jrg Henkel |
| 2005 | Crowdedness-balanced multilevel partitioning for uniform resource utilization. | Yongseok Cheon, Martin D. F. Wong |
| 2005 | Panel III: EDA market in China. | David Chen, Nancy Wu, Wayne Dai, Jun Tan, Weiping Liu, Hao Min, Jian-yue Pan |