| 2005 | Increasing FPGA resilience against soft errors using task duplication. | Guangyu Chen, Feihui Li, Mahmut T. Kandemir, I. Demirkiran |
| 2005 | Compiler-directed selective data protection against soft errors. | G. Chen, Mahmut T. Kandemir, Mary Jane Irwin, Gokhan Memik |
| 2005 | Optimizing embedded applications using programmer-inserted hints. | G. Chen, Mahmut T. Kandemir |
| 2005 | Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? | Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen |
| 2005 | Floorplanning for 3-D VLSI design. | Lei Cheng, Liang Deng, Martin D. F. Wong |
| 2005 | Optimal module and voltage assignment for low-power. | Deming Chen, Jason Cong, Junjuan Xu |
| 2005 | Multilevel full-chip gridless routing considering optical proximity correction. | Tai-Chen Chen, Yao-Wen Chang |
| 2005 | A multi-level transmission line network approach for multi-giga hertz clock distribution. | Hongyu Chen, Chung-Kuan Cheng |
| 2005 | Efficiently generating test vectors with state pruning. | Ying Chen, Dennis Abts, David J. Lilja |
| 2005 | Design of a high performance FFT processor based on FPGA. | Chu Chao, Qin Zhang, Yingke Xie, Chengde Han |
| 2005 | Functionality directed clustering for low power MTCMOS design. | Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu |
| 2005 | Supporting sequential assumptions in hybrid verification. | Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma |
| 2005 | Post-layout logic duplication for synthesis of domino circuits with complex gates. | Aiqun Cao, Ruibing Lu, Cheng-Kok Koh |
| 2005 | Library cell layout with Alt-PSM compliance and composability. | Ke Cao, Puneet Dhawan, Jiang Hu |
| 2005 | Relaxed hierarchical power/ground grid analysis. | Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu |
| 2005 | Multi-metric and multi-entity characterization of applications for early system design exploration. | Lukai Cai, Andreas Gerstlauer, Daniel Gajski |
| 2005 | Comparing high-level modeling approaches for embedded system design. | Lisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flvio Rech Wagner, Carlos Eduardo Pereira, Ricardo Reis |
| 2005 | Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. | Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya |
| 2005 | Substrate noise modeling in early floorplanning of MS-SOCs. | Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang |
| 2005 | Leakage power: trends, analysis and avoidance. | David T. Blaauw, Anirudh Devgan, Farid N. Najm |
| 2005 | Static power minimization in current-mode circuits. | M. S. Bhat, H. S. Jamadagni |
| 2005 | Exploiting temporal idleness to reduce leakage power in programmable architectures. | Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia |
| 2005 | Scalable interprocedural register allocation for high level synthesis. | Rami Beidas, Jianwen Zhu |
| 2005 | Wire congestion and thermal aware 3D global placement. | Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim |
| 2005 | Integration of supercubing and learning in a SAT solver. | Domagoj Babic, Alan J. Hu |