| 2005 | A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. | Raid Ayoub, Alex Orailoglu |
| 2005 | Opportunities and challenges for better than worst-case design. | Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge |
| 2005 | A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
| 2005 | Placement stability metrics. | Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz |
| 2005 | Dynamic symmetry-breaking for improved Boolean optimization. | Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah |
| 2005 | Dynamic power management using on demand paging for networked embedded systems. | Yuvraj Agarwal, Curt Schurgers, Rajesh Gupta |
| 2005 | Achieving continuous V | Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan |
| 2005 | An efficient combinationality check technique for the synthesis of cyclic combinational circuits. | Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang |
| 2005 | Statistical modeling of cross-coupling effects in VLSI interconnects. | Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
| 2005 | A formalism for functionality preserving system level transformations. | Samar Abdi, Daniel Gajski |
| 2005 | Three-dimensional place and route for FPGAs. | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
| 2004 | Efficient octilinear Steiner tree construction based on spanning graphs. | Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang |
| 2004 | Space-planning: placement of modules with controlled empty area by single-sequence. | Xuliang Zhang, Yoji Kajitani |
| 2004 | Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification. | Rouying Zhan, Haigang Feng, Qiong Wu, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang |
| 2004 | An SoC architecture and its design methodology using unifunctional heterogeneous processor array. | Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2004 | Temporal floorplanning using 3D-subTCG. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen |
| 2004 | Embedded software generation from system level design languages. | Haobo Yu, Rainer Dmer, Daniel Gajski |
| 2004 | A low power asynchronous Java processor for contactless smart card. | Chun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-Fat Chan, Kong-Pang Pun |
| 2004 | Timing optimization by replacing flip-flops to latches. | Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura |
| 2004 | Development of a waveform sampling front-end ASIC for PET. | Jung-Yeol Yeom, T. Ishitsu, Hiroyuki Takahashi |
| 2004 | Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. | Yuji Yano, Tetsushi Koide, Hans Jrgen Mattausch |
| 2004 | Timing-constrained congestion-driven global routing. | Jin-Tai Yan, Shun-Hua Lin |
| 2004 | An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction. | Liu Yang, Xiaobo Guo, Zeyi Wang |
| 2004 | TranGen: a SAT-based ATPG for path-oriented transition faults. | Kai Yang, Kwang-Ting Cheng, Li-C. Wang |
| 2004 | A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. | Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu |