| 2025 | Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuation. | Koji Kikuta, Takashi Hisakado, Mahfuzul Islam |
| 2025 | DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations. | Sadaf Khan, Zhengyuan Shi, Ziyang Zheng, Min Li, Qiang Xu |
| 2025 | Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K. | Takuma Kawakami, Takashi Sato, Hiromitsu Awano |
| 2025 | Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models. | Wei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang |
| 2025 | Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes. | Sota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka |
| 2025 | SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. | Xilong Kang, Qingwen Wei, Ningyuan Li, Xingyu Xu, Hao Cai, Bo Liu |
| 2025 | RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword Spotting. | Gunil Kang, Dahoon Park, Hojin Lee, Sangwoo Jung, Jiyong Park, Jung Gyu Min, Youngjoo Lee, Jaeha Kung |
| 2025 | A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. | Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han |
| 2025 | A High-Density Hybrid Buck Converter with a Charge Converging Phase Reducing Inductor Current for 12V Power Supply Systems. | Yichao Ji, Ji Jin, Lin Cheng |
| 2025 | Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. | Zijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi |
| 2025 | Boosting the Performance of Transistor-Level Circuit Simulation with GNN. | Jiqing Jiang, Yongqiang Duan, Zhou Jin |
| 2025 | ADEPT-Z: Zero-Shot Automated Circuit Topology Search for Pareto-Optimal Photonic Tensor Cores. | Ziyang Jiang, Pingchuan Ma, Meng Zhang, Z. Rena Huang, Jiaqi Gu |
| 2025 | A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing. | Limin Jiang, Yi Shi, Yintao Liu, Qingyu Deng, Siyi Xu, Yihao Shen, Fangfang Ye, Shan Cao, Zhiyuan Jiang |
| 2025 | A Computation and Energy Efficient Hardware Architecture for SSL Acceleration. | Huidong Ji, Sheng Li, Yue Cao, Chen Ding, Jiawei Xu, Qitao Tan, Jun Liu, Ao Li, Xulong Tang, Lirong Zheng, Geng Yuan, Zhuo Zou |
| 2025 | PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. | Eunsol Jeong, Taewhan Kim, Heechun Park |
| 2025 | Efficient Key Switching Accelerator for Fully Homomorphic Encryption. | Seoyoon Jang, Sungjin Park, Dongsuk Jeon |
| 2025 | WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory. | Seoyoon Jang, Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee, Hankyu Chi, Wookjin Shin, Changhyun Pyo, Jaeha Kim, Dongsuk Jeon |
| 2025 | A Hybrid Machine Learning and Numeric Optimization Approach to Analog Circuit Deobfuscation. | Dipali Deepak Jain, Guangwei Zhao, Rajesh Kumar Datta, Kaveh Shamsi |
| 2025 | Cryo-Compact Modeling Based on Sparse Gaussian Process. | Tetsuro Iwasaki, Takashi Sato, Michihiro Shintani |
| 2025 | Hardware Trojan Detection by Fine-grained Power Domain Partitioning. | Takahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi |
| 2025 | DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. | Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin |
| 2025 | MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision Training. | Leran Huang, Yongpan Liu, Xinyuan Lin, Chenhan Wei, Wenyu Sun, Zengwei Wang, Boran Cao, Chi Zhang, Xiaoxia Fu, Wentao Zhao, Sheng Zhang |
| 2025 | Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. | Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu |
| 2025 | An Edge AI and Adaptive Embedded System Design for Agricultural Robotics Applications. | Chun-Hsian Huang, Zhi-Rui Chen, Huai-Shu Hsu |
| 2025 | LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration. | Shan Huang, Jinhao Li, Zhen Yu, Jiancai Ye, Jiaming Xu, Ningyi Xu, Guohao Dai |