| 2024 | Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators. | Yi Li, Aarti Gupta, Sharad Malik |
| 2024 | TIUP: Effective Processor Verification with Tautology-Induced Universal Properties. | Yufeng Li, Yiwei Ci, Qiusong Yang |
| 2024 | Timing Analysis beyond Complementary CMOS Logic Styles. | Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif |
| 2024 | Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. | Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | Reinforcing the Connection between Analog Design and EDA (Invited Paper). | Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | Towards a Highly Interactive Design-Debug-Verification Cycle. | Lucas Klemmer, Daniel Groe |
| 2024 | Flexible Spatio-Temporal Energy-Efficient Runtime Management. | Robert Khasanov, Marc Dietrich, Jernimo Castrilln |
| 2024 | Resource- and Workload-aware Malware Detection through Distributed Computing in IoT Networks. | Sreenitha Kasarapu, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao |
| 2024 | LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage. | Hye Rim Ji, Jong Seong Kim, Jung Yun Choi, Jee Hyong Lee |
| 2024 | Collaborative Coalescing of Redundant Memory Access for GPU System. | Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu |
| 2024 | SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating. | Fan Jiang, Chengeng Li, Lin Chen, Jiaqi Liu, Wei Zhang, Jiang Xu |
| 2024 | LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing. | Yihong Hu, Nuo Xu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang |
| 2024 | DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. | Guangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang |
| 2024 | ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning. | Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi |
| 2024 | Row Planning and Placement for Hybrid-Row-Height Designs. | Ching-Yao Huang, Wai-Kei Mak |
| 2024 | CTQr: Control and Timing-Aware Qubit Routing. | Ching-Yao Huang, Wai-Kei Mak |
| 2024 | TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation. | Shiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Haomin Li, Li Jiang |
| 2024 | A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. | Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang |
| 2024 | WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR. | En-Ming Huang, Bo-Wun Cheng, Meng-Hsien Lin, Chun-Yi Lee, Tsung Tai Yeh |
| 2024 | TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design. | Chen-Hao Hsu, Xiaoqing Xu, Hao Chen, Dino Ruic, David Z. Pan |
| 2024 | PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage : (Invited Paper). | Yun-Shan Hsieh, Bo-Jun Chen, Po-Chun Huang, Yuan-Hao Chang |
| 2024 | Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation. | Tianshu Hou, Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang, Hai-Bao Chen, Ngai Wong |
| 2024 | Hard Error Correction in STT-MRAM. | Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Gouri Sankar Kar |
| 2024 | An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning. | Guoqing He, Wenjie Ding, Yuyang Ye, Xu Cheng, Qianqian Song, Peng Cao |
| 2024 | Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing. | Christoph Hazott, Florian Stgmller, Daniel Groe |