| 2015 | Analytical placement for rectilinear blocks. | Yasuhiro Takashima |
| 2015 | ASP-DAC 2015 keynote speech II programmable network. | Atsushi Takahara |
| 2015 | Fast statistical analysis of rare failure events for memory circuits in high-dimensional variation space. | Shupeng Sun, Xin Li |
| 2015 | On test syndrome merging for reasoning-based board-level functional fault diagnosis. | Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu |
| 2015 | A flexible hardware barrier mechanism for many-core processors. | Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue |
| 2015 | A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. | Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa |
| 2015 | Microarchitectural-level statistical timing models for near-threshold circuit design. | Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
| 2015 | A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations. | Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram |
| 2015 | Speeding up single pass simulation of PLRUt caches. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2015 | An autonomous decentralized mechanism for energy interchanges with accelerated diffusion based on MCMC. | Yusuke Sakumoto, Ittetsu Taniguchi |
| 2015 | Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. | Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan |
| 2015 | A real-time permutation entropy computation for EEG signals. | Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren |
| 2015 | A 128-way FPGA platform for the acceleration of KLMS algorithm. | Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren |
| 2015 | Gate sizing and threshold voltage assignment for high performance microprocessor designs. | Tiago Reimann, Cliff C. N. Sze, Ricardo Reis |
| 2015 | Two-phase protocol converters for 3D asynchronous 1-of-n data links. | Julian J. H. Pontes, Pascal Vivet, Yvain Thonnart |
| 2015 | Battery-aware mapping optimization of loop nests for CGRAs. | Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2015 | Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. | Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin |
| 2015 | Automatic design for analog/RF front-end system in 802.11ac receiver. | Zhijian Pan, Chuan Qin, Zuochang Ye, Yan Wang |
| 2015 | Electromigration-aware redundant via insertion. | Jiwoo Pak, Bei Yu, David Z. Pan |
| 2015 | Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC. | Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno |
| 2015 | A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. | Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa |
| 2015 | Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. | Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda |
| 2015 | Systems modeling for additional development in automotive E/E architecture. | Hidekazu Nishimura |
| 2015 | An efficient multi-port memory controller for multimedia applications. | Xuan-Thuan Nguyen, Cong-Kha Pham |
| 2015 | Compact modeling of microbatteries using behavioral linearization and model-order reduction. | Mohammed Shemsu Nesro, Lizhong Sun, Ibrahim M. Elfadel |