| 2014 | Sparse statistical model inference for analog circuits under process variations. | Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi |
| 2014 | Task- and network-level schedule co-synthesis of Ethernet-based time-triggered systems. | Licong Zhang, Dip Goswami, Reinhard Schneider, Samarjit Chakraborty |
| 2014 | BOB-router: A new buffering-aware global router with over-the-block routing resources optimization. | Yilin Zhang, Salim Chowdhury, David Z. Pan |
| 2014 | A segmentation-based BISR scheme. | Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi |
| 2014 | Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory. | Hao Yu, Yuhao Wang, Shuai Chen, Wei Fei, Chuliang Weng, Junfeng Zhao, Zhulin Wei |
| 2014 | Efficient simulation-based optimization of power grid with on-chip voltage regulator. | Ting Yu, Martin D. F. Wong |
| 2014 | Time-domain performance bound analysis for analog and interconnect circuits considering process variations. | Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang |
| 2014 | An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. | Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro |
| 2014 | 7.3 Gb/s universal BCH encoder and decoder for SSD controllers. | Hoyoung Yoo, Youngjoo Lee, In-Cheol Park |
| 2014 | General purpose cross-referencing Microfluidic Biochip with reduced pin-count. | Jackson H. C. Yeung, Evangeline F. Y. Young |
| 2014 | Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems. | Yuan Yao, Zhonghai Lu |
| 2014 | Annotation and analysis combined cache modeling for native simulation. | Rongjie Yan, De Ma, Kai Huang, Xiaoxu Zhang, Siwen Xiu |
| 2014 | Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. | Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie |
| 2014 | A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. | Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak |
| 2014 | A fast and provably bounded failure analysis of memory circuits in high dimensions. | Wei Wu, Fang Gong, GengSheng Chen, Lei He |
| 2014 | A topology-based ECO routing methodology for mask cost minimization. | Po-Hsun Wu, Shang-Ya Bai, Tsung-Yi Ho |
| 2014 | Optimal SWAP gate insertion for nearest neighbor quantum circuits. | Robert Wille, Aaron Lye, Rolf Drechsler |
| 2014 | Property Directed Reachability for QF_BV with mixed type atomic reasoning units. | Tobias Welp, Andreas Kuehlmann |
| 2014 | Implicit intermittent fault detection in distributed systems. | Peter Waszecki, Matthias Kauer, Martin Lukasiewycz, Samarjit Chakraborty |
| 2014 | A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. | Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li |
| 2014 | PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices. | Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta |
| 2014 | Walking pads: Fast power-supply pad-placement optimization. | Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan |
| 2014 | Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources. | Xiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak |
| 2014 | Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor. | Cong Wang, Naehyuck Chang, Younghyun Kim, Sangyoung Park, Yongpan Liu, Hyung Gyu Lee, Rong Luo, Huazhong Yang |
| 2014 | Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU. | Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue |