| 2011 | Variation-aware logic mapping for crossbar nano-architectures. | Masoud Zamani, Mehdi Baradaran Tahoori |
| 2011 | Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation model. | Wenjian Yu, Chao Hu, Wangyang Zhang |
| 2011 | Network flow-based simultaneous retiming and slack budgeting for low power design. | Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto |
| 2011 | Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handset. | Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma |
| 2011 | Routing with graphene nanoribbons. | Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen |
| 2011 | Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. | Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan |
| 2011 | Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps. | Hui Xu, Guoyong Shi, Xiaopeng Li |
| 2011 | Rapid layout pattern classification. | Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska |
| 2011 | Robust power gating reactivation by dynamic wakeup sequence throttling. | Tung-Yeh Wu, Shih-Hsin Hu, Jacob A. Abraham |
| 2011 | Parallel cross-layer optimization of high-level synthesis and physical design. | James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng |
| 2011 | Balanced truncation for time-delay systems via approximate Gramians. | Xiang Wang, Qing Wang, Zheng Zhang, Quan Chen, Ngai Wong |
| 2011 | Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. | Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong |
| 2011 | Analog circuit verification by statistical model checking. | Ying-Chih Wang, Anvesh Komuravelli, Paolo Zuliani, Edmund M. Clarke |
| 2011 | From RTL to silicon: The case for automated debug. | Andreas G. Veneris, Brian Keng, Sean Safarpour |
| 2011 | Automatic formal verification of reconfigurable DSPs. | Miroslav N. Velev, Ping Gao |
| 2011 | A low-power management technique for high-performance domino circuits. | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2011 | Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2011 | FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design. | Masaru Takahashi |
| 2011 | Advanced system LSIs for home 3D system. | Takao Suzuki |
| 2011 | Network-on-Chip router design with Buffer-Stealing. | Wan-Ting Su, Jih-Sheng Shen, Pao-Ann Hsiung |
| 2011 | A frequent-value based PRAM memory architecture. | Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie |
| 2011 | Post-routing layer assignment for double patterning. | Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng |
| 2011 | A fast approximation technique for power grid analysis. | Mysore Sriram |
| 2011 | Ultra-low power microcontrollers for portable, wearable, and implantable medical electronics. | Srinivasa R. Sridhara |
| 2011 | EUV lithography: Prospects and challenges. | Sam Sivakumar |