| 2011 | AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors. | Abhishek A. Sinkar, Nam Sung Kim |
| 2011 | Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph. | Tae-ho Shin, Hyunok Oh, Soonhoi Ha |
| 2011 | Device-parameter estimation with on-chip variation sensors considering random variability. | Kenichi Shinkai, Masanori Hashimoto |
| 2011 | Equivalent lumped element models for various n-port Through Silicon Vias networks. | Khaled Salah, Hani F. Ragai, Yehea I. Ismail, Alaa B. El-Rouby |
| 2011 | On the interplay of loop caching, code compression, and cache configuration. | Marisha Rawlins, Ann Gordon-Ross |
| 2011 | An integer programming placement approach to FPGA clock power reduction. | Alireza Rakhshanfar, Jason Helge Anderson |
| 2011 | A low-power triple-mode sigma-delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters. | Dong Qiu, Ting Yi, Zhiliang Hong |
| 2011 | A thermal-aware application specific routing algorithm for Network-on-Chip design. | Zhiliang Qian, Chi-Ying Tsui |
| 2011 | Fast data-cache modeling for native co-simulation. | Hector Posadas, Luis Diaz, Eugenio Villar |
| 2011 | Human++: Wireless autonomous sensor technology for body area networks. | Valer Pop, Ruben de Francisco, Hans W. Pflug, Juan Santana, Hubregt J. Visser, Ruud J. M. Vullers, Harmke de Groot, Bert Gyselinckx |
| 2011 | SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power. | Chi-Chen Peng, Chen Dong, Deming Chen |
| 2011 | NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults. | Sudeep Pasricha, Yong Zou |
| 2011 | OPAL: A multi-layer hybrid photonic NoC for 3D ICs. | Sudeep Pasricha, Shirish Bahirat |
| 2011 | Exploration of VLSI CAD researches for early design rule evaluation. | Chul-Hong Park, David Z. Pan, Kevin Lucas |
| 2011 | An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. | Yu Pang, Katarzyna Radecka, Zeljko Zilic |
| 2011 | Enabling quality-of-service in nanophotonic network-on-chip. | Jin Ouyang, Yuan Xie |
| 2011 | A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. | Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa |
| 2011 | An RTL-to-GDS2 design methodology for advanced system LSI. | Nobuyuki Nishiguchi |
| 2011 | Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliances. | Tatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, Alexandre Courbot, Tsung-Han Lin |
| 2011 | Design and evaluation of variable stages pipeline processor chip. | Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo |
| 2011 | Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems. | Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch |
| 2011 | A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. | Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa |
| 2011 | Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems. | Jingqing Mu, Roman L. Lysecky |
| 2011 | Wire synthesizable global routing for timing closure. | Michael D. Moffitt, Chin Ngai Sze |
| 2011 | A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. | Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young |