| 2011 | Two-terminal resistive switches (memristors) for memory and logic applications. | Wei Lu, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba |
| 2011 | Mathematical limits of parallel computation for embedded systems. | Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden |
| 2011 | Compression-aware capture power reduction for at-speed testing. | Jia Li, Qiang Xu, Dong Xiang |
| 2011 | A resilient on-chip router design through data path salvaging. | Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li |
| 2011 | Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. | Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li |
| 2011 | A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms. | Xuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Tan |
| 2011 | On-chip hybrid power supply system for wireless sensor nodes. | Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang |
| 2011 | Negotiation-based layer assignment for via count and via overflow minimization. | Wen-Hao Liu, Yih-Lang Li |
| 2011 | Low power discrete voltage assignment under clock skew scheduling. | Li Li, Jian Sun, Yinghai Lu, Hai Zhou, Xuan Zeng |
| 2011 | Battery-aware task scheduling in distributed mobile systems with lifetime constraint. | Jiayin Li, Meikang Qiu, Jianwei Niu, Tianzhou Chen |
| 2011 | Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs. | Jing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu |
| 2011 | Simultaneous redundant via insertion and line end extension for yield optimization. | Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao |
| 2011 | An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs. | Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho |
| 2011 | An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. | Kyoung-Hwan Lim, Taewhan Kim |
| 2011 | Template-based memory access engine for accelerators in SoCs. | Bin Li, Zhen Fang, Ravi R. Iyer |
| 2011 | Equivalence checking of scheduling with speculative code transformations in high-level synthesis. | Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou |
| 2011 | On-chip dynamic signal sequence slicing for efficient post-silicon debugging. | Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita |
| 2011 | A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. | Yongho Lee, Taewhan Kim |
| 2011 | NBTI-aware power gating design. | Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang |
| 2011 | Row-based area-array I/O design planning in concurrent chip-package design flow. | Ren-Jie Lee, Hung-Ming Chen |
| 2011 | On applying erroneous clock gating conditions to further cut down power. | Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu |
| 2011 | Thermally optimal stop-go scheduling of task graphs with real-time constraints. | Pratyush Kumar, Lothar Thiele |
| 2011 | Run-time adaptable on-chip thermal triggers. | Pratyush Kumar, David Atienza |
| 2011 | Reconfiguration-aware real-time scheduling under QoS constraint. | Hessam Kooti, Deepak Mishra, Eli Bozorgzadeh |
| 2011 | An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |