| 2024 | INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding. | Fangxin Liu, Ning Yang, Zhiyan Song, Zongwu Wang, Haomin Li, Shiyuan Huang, Zhuoran Song, Songwen Pei, Li Jiang |
| 2024 | PowerRChol: Efficient Power Grid Analysis Based on Fast Randomized Cholesky Factorization. | Zhiqiang Liu, Wenjian Yu |
| 2024 | NeuroSelect: Learning to Select Clauses in SAT Solvers. | Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu |
| 2024 | Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. | Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han |
| 2024 | Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory. | Jialong Liu, Wenjun Tang, Deyun Chen, Chen Jiang, Huazhong Yang, Xueqing Li |
| 2024 | Effectively Sanitizing Embedded Operating Systems. | Jianzhong Liu, Yuheng Shen, Yiru Xu, Hao Sun, Heyuan Shi, Yu Jiang |
| 2024 | MoC: A Morton-Code-Based Fine-Grained Quantization for Accelerating Point Cloud Neural Networks. | Xueyuan Liu, Zhuoran Song, Hao Chen, Xing Li, Xiaoyao Liang |
| 2024 | PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis. | Dajiang Liu, Decai Pan, Xiao Xiong, Jiaxing Shang, Shouyi Yin |
| 2024 | SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm. | Meng Liu, Shuai Li, Fei Xiao, Ruijie Wang, Chunxue Liu, Liang Wang |
| 2024 | Auto-ISP: An Efficient Real-Time Automatic Hyperparameter Optimization Framework for ISP Hardware System. | Jiaming Liu, Zihao Liu, Xuan Huang, Ruoxi Zhu, Qi Zheng, Zhijian Hao, Tao Liu, Jun Tao, Yibo Fan |
| 2024 | Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture. | Changxu Liu, Hao Zhou, Lan Yang, Jiamin Xu, Patrick Dai, Fan Yang |
| 2024 | TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments. | Ziyu Liu, Tong Zhou, Yukui Luo, Xiaolin Xu |
| 2024 | Enabling Low Latency for ECQF based Flow Aggregation Scheduling in Time-Sensitive Networking. | Ping Liu, Tong Zhang, Xiaoqin Feng, Yanying Ma, Fengyuan Ren |
| 2024 | Late Breaking Result: AQFP-aware Binary Neural Network Architecture Search. | Zhengang Li, Xuan Shen, Geng Yuan, Masoud Zabihi, Tomoharu Yamauchi, Yanzhi Wang, Olivia Chen |
| 2024 | FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference. | Chenqi Lin, Tianshi Xu, Zebin Yang, Runsheng Wang, Ru Huang, Meng Li |
| 2024 | Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of DNNs. | Ning Lin, Shaocong Wang, Yue Zhang, Yangu He, Kwunhang Wong, Arindam Basu, Dashan Shang, Xiaoming Chen, Zhongrui Wang |
| 2024 | Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs. | Chia-Wei Lin, Jing-Yao Weng, I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu, Mark Po-Hung Lin |
| 2024 | FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA. | Xuanda Lin, Huinan Tian, Wenxiao Xue, Lanqi Ma, Jialin Cao, Manting Zhang, Jun Yu, Kun Wang |
| 2024 | Size-Optimized Depth-Constrained Large Parallel Prefix Circuits. | Shiju Lin, Bentian Jiang, Weihua Sheng, Evangeline F. Y. Young |
| 2024 | GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. | Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong |
| 2024 | WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. | Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu |
| 2024 | SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning. | Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Huawei Li |
| 2024 | Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI). | Mengchu Li, Hanchen Gu, Yushen Zhang, Siyuan Liang, Hudson Gasvoda, Rana Altay, Ismail Emre Araci, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann |
| 2024 | PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency. | Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan |
| 2024 | LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design. | Siyuan Liang, Yushen Zhang, Rana Altay, Hudson Gasvoda, Mengchu Li, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho |