| 2026 | ASPDAC | Au-MEDAL: Adaptable Grid Router with Metal Edge Detection And Layer Integration. | Andrew B. Kahng, Seokhyeong Kang, Sehyeon Kim, Jakang Lee, Dooseok Yoon |
| 2026 | ISCAS | LSMC Meets GPU Acceleration: Scalable and High-Quality Multi-Row Detailed Placement. | Andrew B. Kahng, Jason Liang, Zhiang Wang |
| 2025 | ASPDAC | Use Cases and Deployment of ML in IC Physical Design. | Amur Ghose, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Bodhisatta Pramanik, Zhiang Wang, Dooseok Yoon |
| 2025 | FCCM | A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. | Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib |
| 2025 | ICCAD | SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing. | Chung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin |
| 2025 | ICCAD | Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem. | Vidya A. Chhabria, Amur Ghose, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Zhiang Wang, Bing-Yue Wu |
| 2024 | AAAI | NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem. | Andrew B. Kahng, Robert R. Nerem, Yusu Wang, Chien-Yi Yang |
| 2024 | DAC | PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. | Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, Seonghyeon Park, Bodhisatta Pramanik |
| 2024 | DATE | Improvement of Mixed Track - Height Standard-Cell Placement. | Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon |
| 2024 | ICCAD | Strengthening the Foundations for IC Physical Design and ML EDA Research. | Vidya A. Chhabria, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Bing-Yue Wu, Dooseok Yoon |
| 2024 | ICCAD | Placement Tomography-Based Routing Blockage Generation for DRV Hotspot Mitigation. | Andrew B. Kahng, Sayak Kundu, Dooseok Yoon |
| 2024 | VTS | OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. | Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu |
| 2023 | ICCAD | An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design. | Ismail Bustany, Grigor Gasparyan, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang |
| 2023 | ICCAD | Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. | Jiang Hu, Andrew B. Kahng |
| 2023 | ICCAD | Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research. | Jinwook Jung, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Dooseok Yoon |
| 2022 | ICCAD | SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement. | Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang |
| 2022 | ICCAD | IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA. | Jinwook Jung, Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang |
| 2022 | ICCAD | A Mixed Open-Source and Proprietary EDA Commons for Education and Prototyping. | Andrew B. Kahng |
| 2021 | ICCAD | DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo |
| 2021 | ICCAD | VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. | Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng |
| 2021 | ICCAD | METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session Paper. | Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan |
| 2021 | ICCD | CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. | Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo |
| 2020 | ASPDAC | Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. | Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu |
| 2020 | DAC | The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing. | Andrew B. Kahng, Lutong Wang, Bangqi Xu |
| 2020 | ICCAD | DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo |
| 2020 | VLSID | Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update. | Abdelrahman Hosny, Andrew B. Kahng |
| 2019 | ASPDAC | Learning-based prediction of package power delivery network quality. | Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu |
| 2019 | ASPDAC | Finding placement-relevant clusters with fast modularity-based clustering. | Mateus Fogaa, Andrew B. Kahng, Ricardo Reis, Lutong Wang |
| 2019 | ASPDAC | Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI. | Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang |
| 2019 | DAC | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. | Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaa, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu |
| 2019 | DATE | Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI. | Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang, Chutong Yang |
| 2019 | DATE | Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology. | Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu |
| 2019 | DATE | "Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design. | Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul, Shangyuan Tong |
| 2019 | ICCAD | DATC RDF-2019: Towards a Complete Academic Reference Design Flow. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo |
| 2019 | ICCAD | IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. | Chia-Tung Ho, Andrew B. Kahng |
| 2019 | ICCAD | Looking Into the Mirror of Open Source: Invited Paper. | Andrew B. Kahng |
| 2018 | ASPDAC | New directions for learning-based IC design tools and methodologies. | Andrew B. Kahng |
| 2018 | DAC | A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. | Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky |
| 2018 | DAC | Reducing time and effort in IC implementation: a roadmap of challenges and solutions. | Andrew B. Kahng |
| 2018 | DATE | Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. | Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful A. Mojumder, Tiansheng Zhang |
| 2018 | ICCAD | A cross-layer methodology for design and optimization of networks in 2.5D systems. | Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Vaishnav Srinivas |
| 2018 | ICCAD | TritonRoute: an initial detailed router for advanced VLSI technologies. | Andrew B. Kahng, Lutong Wang, Bangqi Xu |
| 2018 | ICCD | Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis. | Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul |
| 2017 | ASPDAC | Floorplan and placement methodology for improved energy reduction in stacked power-domain design. | Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, Jos Pineda de Gyvez |
| 2017 | DAC | Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. | Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang |
| 2017 | ICCAD | Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. | Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu |
| 2017 | ICCD | ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning. | Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng |
| 2016 | ASPDAC | Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. | Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo |
| 2016 | ASPDAC | Learning-based prediction of embedded memory timing failures during initial floorplan design. | Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath |
| 2016 | DAC | Comprehensive optimization of scan chain timing during late-stage IC implementation. | Kun Young Chung, Andrew B. Kahng, Jiajia Li |
| 2016 | DATE | Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems. | Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang |
| 2016 | DATE | Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. | Kwangsoo Han, Andrew B. Kahng, Jiajia Li |
| 2016 | ICCAD | Measuring progress and value of IC implementation technology. | Andrew B. Kahng, Hyein Lee, Jiajia Li |
| 2016 | ICCAD | Improved flop tray-based design implementation for power reduction. | Andrew B. Kahng, Jiajia Li, Lutong Wang |
| 2016 | ICCD | BEOL stack-aware routability prediction from placement using data mining techniques. | Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi |
| 2015 | DAC | 3DIC benefit estimation and implementation guidance from 2DIC implementation. | Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi |
| 2015 | DAC | Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. | Kwangsoo Han, Andrew B. Kahng, Hyein Lee |
| 2015 | DAC | A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. | Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee |
| 2015 | DAC | New game, new goal posts: a recent history of timing closure. | Andrew B. Kahng |
| 2015 | ICCAD | Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. | Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li |
| 2015 | ICCAD | Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. | Sorin Dobre, Andrew B. Kahng, Jiajia Li |
| 2015 | ICCAD | Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. | Kwangsoo Han, Andrew B. Kahng, Hyein Lee |
| 2015 | ICCAD | Evolving EDA Beyond its E-Roots: An Overview. | Andrew B. Kahng, Farinaz Koushanfar |
| 2015 | ICCAD | Toward Metrics of Design Automation Research Impact. | Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins |
| 2015 | ITC | Modeling the future of semiconductors (and test!). | Andrew B. Kahng |
| 2014 | DATE | A deep learning methodology to proliferate golden signoff timing. | Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan |
| 2014 | DATE | Mission profile aware IC design - A case study. | Goeran Jerke, Andrew B. Kahng |
| 2014 | DATE | Co-optimization of memory BIST grouping, test scheduling, and logic placement. | Andrew B. Kahng, Ilgweon Kang |
| 2014 | ICCAD | Benchmarking of mask fracturing heuristics. | Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria |
| 2014 | ICCD | ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. | Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath |
| 2014 | ICCD | Improved signoff methodology with tightened BEOL corners. | Tuck-Boon Chan, Sorin Dobre, Andrew B. Kahng |
| 2014 | ICCD | The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. | Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto |
| 2013 | ASPDAC | Optimization of overdrive signoff. | Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath |
| 2013 | ASPDAC | On potential design impacts of electromigration awareness. | Andrew B. Kahng, Siddhartha Nath, Tajana Rosing |
| 2013 | DAC | The ITRS design technology and system drivers roadmap: process and status. | Andrew B. Kahng |
| 2013 | DAC | Smart non-default routing for clock power reduction. | Andrew B. Kahng, Seokhyeong Kang, Hyein Lee |
| 2013 | DATE | Impact of adaptive voltage scaling on aging-aware signoff. | Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng |
| 2013 | DATE | Active-mode leakage reduction with data-retained power gating. | Andrew B. Kahng, Seokhyeong Kang, Bongil Park |
| 2013 | DATE | Enhanced metamodeling techniques for high-dimensional IC design estimation problems. | Andrew B. Kahng, Bill Lin, Siddhartha Nath |
| 2013 | ICCAD | High-performance gate sizing with a signoff timer. | Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar |
| 2013 | ICCAD | Incremental multiple-scan chain ordering for ECO flip-flop insertion. | Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath |
| 2013 | ICCD | Statistical analysis and modeling for error composition in approximate computation circuits. | Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
| 2012 | DAC | Accuracy-configurable adder for approximate arithmetic designs. | Andrew B. Kahng, Seokhyeong Kang |
| 2012 | DAC | Explicit modeling of control and data for improved NoC router estimation. | Andrew B. Kahng, Bill Lin, Siddhartha Nath |
| 2012 | DATE | MAPG: Memory access power gating. | Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong |
| 2012 | ICCAD | Tunable sensors for process-aware voltage scaling. | Tuck-Boon Chan, Andrew B. Kahng |
| 2012 | ICCAD | Sensitivity-guided metaheuristics for accurate discrete gate sizing. | Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov |
| 2012 | ICCAD | CACTI-IO: CACTI with off-chip power-area-timing models. | Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas |
| 2012 | ISLPED | TAP: token-based adaptive power gating. | Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong |
| 2010 | ASPDAC | Slack redistribution for graceful degradation under voltage overscaling. | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
| 2010 | ASPDAC | Improved on-chip router analytical power and area modeling. | Andrew B. Kahng, Bill Lin, Kambiz Samadi |
| 2010 | DAC | Eyecharts: constructive benchmarking of gate sizing heuristics. | Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma |
| 2010 | DAC | Recovery-driven design: a power minimization methodology for error-tolerant processor modules. | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
| 2010 | DAC | Trace-driven optimization of networks-on-chip configurations. | Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam |
| 2010 | HPCA | Designing a processor from the ground up to allow voltage/reliability tradeoffs. | Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori |
| 2010 | ICCAD | Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations. | Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam |
| 2009 | ASPDAC | Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. | Kwangok Jeong, Andrew B. Kahng |
| 2009 | DATE | ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. | Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi |
| 2009 | DSD | Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. | Ayse K. Coskun, Andrew B. Kahng, Tajana Simunic Rosing |
| 2009 | ICCAD | Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. | Mohit Gupta, Kwangok Jeong, Andrew B. Kahng |
| 2008 | ASPDAC | Interconnect modeling for improved system-level design optimization. | Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma |
| 2008 | ASPDAC | Investigation of diffusion rounding for post-lithography analysis. | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester |
| 2008 | DAC | Bounded-lifetime integrated circuits. | Puneet Gupta, Andrew B. Kahng |
| 2008 | DAC | Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. | Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao |
| 2008 | DAC | DFM in practice: hit or hype? | Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh |
| 2008 | ICCAD | Layout decomposition for double patterning lithography. | Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao |
| 2007 | ASPDAC | A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. | Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman |
| 2007 | DAC | Line-End Shortening is Not Always a Failure. | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester |
| 2007 | DATE | Design challenges at 65nm and beyond. | Andrew B. Kahng |
| 2007 | ICCAD | Exploiting STI stress for performance. | Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu |
| 2007 | ICCD | Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. | Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu |
| 2007 | ISLPED | Detailed placement for leakage reduction using systematic through-pitch variation. | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
| 2006 | DAC | Timing-driven Steiner trees are (practically) free. | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
| 2006 | DAC | CAD challenges for leading-edge multimedia designs. | Andrew B. Kahng |
| 2006 | DAC | DFM: where's the proof of value? | Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan |
| 2006 | DAC | Standard cell library optimization for leakage reduction. | Saumil Shah, Puneet Gupta, Andrew B. Kahng |
| 2006 | DATE | Lens aberration aware timing-driven placement. | Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang |
| 2006 | ICCAD | Fill for shallow trench isolation CMP. | Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky |
| 2006 | ICCD | Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. | Rasit Onur Topaloglu, Andrew B. Kahng |
| 2006 | VLSID | Efficient Design and Analysis of Robust Power Distribution Meshes. | Puneet Gupta, Andrew B. Kahng |
| 2005 | ASPDAC | Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? | Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen |
| 2005 | ASPDAC | Detailed placement for improved depth of focus and CD control. | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park |
| 2005 | DAC | Power-aware placement. | Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang |
| 2005 | DAC | Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
| 2005 | DATE | Bright-Field AAPSM Conflict Detection and Correction. | Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky |
| 2005 | ICCAD | Fast and efficient phase conflict detection and correction in standard-cell layouts. | Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu |
| 2005 | ICCAD | Intrinsic shortest path length: a new, accurate a priori wirelength estimator. | Andrew B. Kahng, Sherief Reda |
| 2005 | ICCAD | Architecture and details of a high quality, large-scale analytical placer. | Andrew B. Kahng, Sherief Reda, Qinke Wang |
| 2005 | ICCD | Supply Voltage Degradation Aware Analytical Placement. | Andrew B. Kahng, Bao Liu, Qinke Wang |
| 2005 | ISLPED | Defocus-aware leakage estimation and control. | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
| 2004 | ASPDAC | Optimal planning for mesh-based power distribution. | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang |
| 2004 | ASPDAC | Combinatorial group testing methods for the BIST diagnosis problem. | Andrew B. Kahng, Sherief Reda |
| 2004 | DAC | Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. | Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier |
| 2004 | DAC | Toward a methodology for manufacturability-driven design rule exploration. | Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang |
| 2004 | DAC | Selective gate-length biasing for cost-effective runtime leakage control. | Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
| 2004 | DAC | Placement feedback: a concept and method for better min-cut placements. | Andrew B. Kahng, Sherief Reda |
| 2004 | DATE | Boosting: Min-Cut Placement with Improved Signal Delay. | Andrew B. Kahng, Igor L. Markov, Sherief Reda |
| 2004 | ICCAD | An analytic placer for mixed-size placement and timing-driven placement. | Andrew B. Kahng, Qinke Wang |
| 2004 | VLSID | Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. | Puneet Gupta, Andrew B. Kahng |
| 2003 | ASPDAC | Routing-aware scan chain ordering. | Puneet Gupta, Andrew B. Kahng, Stefanus Mantik |
| 2003 | ASPDAC | Highly scalable algorithms for rectilinear and octilinear Steiner trees. | Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
| 2003 | DAC | An algebraic multigrid solver for analytical placement with layout based clustering. | Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu |
| 2003 | DAC | Performance-impact limited area fill synthesis. | Yu Chen, Puneet Gupta, Andrew B. Kahng |
| 2003 | DAC | A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. | Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang |
| 2003 | DAC | Nanometer design: place your bets. | Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf |
| 2003 | DATE | Area Fill Generation With Inherent Data Volume Reduction. | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng |
| 2003 | DATE | A Novel Metric for Interconnect Architecture Performance. | Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu |
| 2003 | ICCAD | The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao |
| 2003 | ICCAD | Manufacturing-Aware Physical Design. | Puneet Gupta, Andrew B. Kahng |
| 2003 | ICCAD | Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. | Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma |
| 2003 | ICCAD | Evaluation of Placement Techniques for DNA Probe Array Layout. | Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky |
| 2003 | ICCD | Design Flow Enhancements for DNA Arrays. | Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky |
| 2003 | RECOMB | Engineering a scalable placement heuristic for DNA probe arrays. | Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky |
| 2002 | DAC | Tools or users: which is the bigger bottleneck? | Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven |
| 2002 | ICCAD | Non-tree routing for reliability and yield improvement. | Andrew B. Kahng, Bao Liu, Ion I. Mandoiu |
| 2002 | VLSID | Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. | Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
| 2002 | WABI | Border Length Minimization in DNA Array Design. | Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky |
| 2001 | ASPDAC | Toward better wireload models in the presence of obstacles. | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt |
| 2001 | ASPDAC | Hierarchical dummy fill for process uniformity. | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
| 2001 | ASPDAC | Provably good global buffering by multi-terminal multicommodity flow approximation. | Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky |
| 2001 | ASPDAC | Design technology productivity in the DSM era (invited talk). | Andrew B. Kahng |
| 2001 | ASPDAC | New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. | Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky |
| 2001 | ASPDAC | Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. | Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori |
| 2001 | DAC | Panel: Is Nanometer Design Under Control? | Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang |
| 2001 | ICCAD | Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. | Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky |
| 2001 | WADS | Practical Approximation Algorithms for Separable Packing Linear Programs. | Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky |
| 2000 | ASPDAC | Improved algorithms for hypergraph bipartitioning. | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
| 2000 | ASPDAC | Monte-Carlo algorithms for layout density control. | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
| 2000 | DAC | GTX: the MARCO GSRC technology extrapolation system. | Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester |
| 2000 | DAC | Can recursive bisection alone produce routable placements? | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
| 2000 | DAC | Practical iterated fill synthesis for CMP uniformity. | Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky |
| 2000 | DAC | METRICS: a system architecture for design process optimization. | Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges |
| 2000 | DAC | On switch factor based analysis of coupled | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto |
| 2000 | DAC | EDA meets.COM (panel session): how E-services will change the EDA business model. | Jennifer Smith, Tom Quan, Andrew B. Kahng |
| 2000 | ICCAD | Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester |
| 2000 | ICCAD | Provably Good Global Buffering Using an Available Buffer Block Plan. | Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky |
| 2000 | ICCAD | On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. | Andrew B. Kahng, Stefanus Mantik |
| 1999 | ALENEX | Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
| 1999 | ASPDAC | Function Smoothing with Applications to VLSI Layout. | Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov |
| 1999 | ASPDAC | New Multilevel and Hierarchical Algorithms for Layout Density Control. | Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky |
| 1999 | ASPDAC | Optimization of Linear Placements for Wirelength Minimization with Free Sites. | Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky |
| 1999 | DAC | Effective Iterative Techniques for Fingerprinting Design IP. | Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong |
| 1999 | DAC | Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. | Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov |
| 1999 | DAC | Hypergraph Partitioning with Fixed Vertices. | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
| 1999 | DAC | Subwavelength Lithography and Its Potential Impact on Design and EDA. | Andrew B. Kahng, Y. C. Pati |
| 1999 | DAC | Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). | Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser |
| 1999 | ICCAD | The associative-skew clock routing problem. | Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky |
| 1999 | ICCAD | Copy detection for intellectual property protection of VLSI designs. | Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong |
| 1999 | VLSID | Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. | Andrew B. Kahng |
| 1999 | VLSID | Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. | Andrew B. Kahng, Sudhakar Muddu |
| 1999 | VLSID | Interconnect Optimization Strategies for High-Performance VLSI Designs. | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto |
| 1999 | VLSID | New and Exact Filling Algorithms for Layout Density Control. | Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky |
| 1999 | WADS | The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout. | Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Alexander Zelikovsky |
| 1998 | DAC | Watermarking Techniques for Intellectual Property Protection. | Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe |
| 1998 | DAC | Robust IP Watermarking Methodologies for Physical Design. | Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe |
| 1998 | DATE | Interconnect Tuning Strategies for High-Performance Ics. | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma |
| 1997 | DAC | Multilevel Circuit Partitioning. | Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng |
| 1997 | DAC | Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. | Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen |
| 1997 | DAC | More Practical Bounded-Skew Clock Routing. | Andrew B. Kahng, Chung-Wen Albert Tsao |
| 1996 | DAC | Analysis of RC Interconnections Under Ramp Input. | Andrew B. Kahng, Sudhakar Muddu |
| 1996 | ICCAD | Analytical delay models for VLSI interconnects under ramp input. | Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
| 1995 | DAC | Quantified Suboptimality of VLSI Layout Heuristics. | Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng |
| 1995 | DAC | On the Bounded-Skew Clock and Steiner Routing Problems. | Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao |
| 1995 | DATE | When clusters meet partitions: new density-based methods for circuit decomposition. | Dennis J.-H. Huang, Andrew B. Kahng |
| 1995 | FPGA | Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. | Dennis J.-H. Huang, Andrew B. Kahng |
| 1995 | ICCAD | Bounded-skew clock and Steiner routing under Elmore delay. | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
| 1995 | IROS | Cooperative mobile robotics: antecedents and directions. | Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng, F. Meng |
| 1994 | DAC | Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. | Charles J. Alpert, Andrew B. Kahng |
| 1994 | DAC | Rectilinear Steiner Trees with Minimum Elmore Delay. | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins |
| 1994 | DAC | Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. | Andrew B. Kahng, Sudhakar Muddu |
| 1994 | ICCAD | A general framework for vertex orderings, with applications to netlist clustering. | Charles J. Alpert, Andrew B. Kahng |
| 1994 | ICCAD | Low-cost single-layer clock trees with exact zero Elmore delay skew. | Andrew B. Kahng, Chung-Wen Albert Tsao |
| 1993 | DAC | Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. | Charles J. Alpert, Andrew B. Kahng |
| 1993 | DAC | High-Performance Routing Trees With Identified Critical Sinks. | Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins |
| 1993 | ICCD | Fidelity and Near-Optimality of Elmore-Based Routing Constructions. | Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins |
| 1993 | ISCAS | Minimum Density Interconneciton Trees. | Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh |
| 1993 | ISCAS | A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. | Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng |
| 1993 | ISCAS | Simulated annealing of neural networks: The 'cooling' strategy reconsidered. | Kenneth D. Boese, Andrew B. Kahng |
| 1992 | DAC | Net Partitions Yield Better Module Partitions. | Jason Cong, Lars W. Hagen, Andrew B. Kahng |
| 1992 | ICCAD | A new approach to effective circuit clustering. | Lars W. Hagen, Andrew B. Kahng |
| 1992 | ICCD | An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. | Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen |
| 1991 | DAC | High-Performance Clock Routing Based on Recursive Geometric Aatching. | Andrew B. Kahng, Jason Cong, Gabriel Robins |
| 1991 | ICCAD | Fast Spectral Methods for Ratio Cut Partitioning and Clustering. | Lars W. Hagen, Andrew B. Kahng |
| 1991 | ICCD | Performance-Driven Global Routing for Cell Based ICs. | Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong |
| 1991 | ICCD | An Effective Analog Approach to Steiner Routing. | Andrew B. Kahng |
| 1990 | ICCAD | A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. | Andrew B. Kahng, Gabriel Robins |
| 1989 | DAC | Fast Hypergraph Partition. | Andrew B. Kahng |