| 2026 | ASPDAC | Subgraph-based Qubit Mapping for Noisy Intermediate-Scale Quantum Computing. | Junyi Gao, Wei-Hsiang Tseng, Yao-Wen Chang |
| 2025 | ASPDAC | Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. | Cheng-Yu Chiang, Yi-Hsien Chiang, Chao-Chi Lan, Yang Hsu, Che-Ming Chang, Shao-Chi Huang, Sheng-Hua Wang, Yao-Wen Chang, Hung-Ming Chen |
| 2025 | ASPDAC | Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models. | Wei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang |
| 2025 | ASPDAC | Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine Learning. | Chao-Chi Lan, Chuan-Chi Su, Yuan-Hsiang Lu, Yao-Wen Chang |
| 2025 | DAC | Clearance-Constrained PCB Global Placement with Heterogeneous Components. | Yan-Jen Chen, Wei-Kai Huang, Chung-Ting Tsai, Chiao-Yu Ou, Yao-Wen Chang |
| 2025 | DAC | Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging. | Min-Hung Chen, Cheng-Yen Li, Chuan-Chi Su, Yao-Wen Chang, Tung-Chieh Chen |
| 2025 | DAC | Late Breaking Results: Scalable GPU-Friendly Parallelization for Sweep-Based Maze Routing. | Cheng-Yu Chiang, Zong-Ying Cai, Chao-Chi Lan, Yan-Jen Chen, Yang Hsu, Yao-Wen Chang, Hung-Ming Chen |
| 2025 | DAC | Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells. | Cheng-Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, Yao-Wen Chang |
| 2025 | DAC | Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-oriented Components. | Chiao-Yu Ou, Yan-Jen Chen, Yao-Wen Chang |
| 2025 | DAC | Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization. | Chien-Hao Tsou, Zhu-Xun Lee, Yao-Wen Chang |
| 2025 | ICCAD | Semidefinite Programming-Based Decoupling Capacitor Placement for Power Distribution Network Optimization. | Zong-Ying Cai, Wei-Han Mao, Yao-Wen Chang, Yang Lu, Jerry Bai, Bin-Chyi Tseng |
| 2025 | ICCAD | Performance-Driven Pre-Assignment Routing for High-Speed Package Designs. | Shao-Hsiang Chen, Zeng-Wei Chen, Po-Jen Lin, Hung-Jen Hsu, Hsin-Ying Lin, Yung-Hsiang Chuang, Huang-Yu Chen, Jim Chang, Yao-Wen Chang |
| 2025 | ICCAD | Advanced Packaging Warpage Modeling with DeepONet-Based Operator Learning. | Shao-Yu Lo, Che-Ming Chang, Yao-Wen Chang |
| 2025 | ICCAD | Parallel Non-Integer Multiple-Cell-Height Node Remapping. | Zong-Han Wu, Bo-Ying Huang, Yu-Chen Chen, Yao-Wen Chang |
| 2025 | QCE | Optimal Qubit Reuse for Quantum Computation with Gate Reordering and Eager Measurement. | Wen-Chen Yu, Tian-Fu Chen, Yu-Hsiang Chan, Jie-Hong R. Jiang, Dah-Wei Chiou, Yao-Wen Chang |
| 2024 | DAC | Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes. | Yan-Jen Chen, Cheng-Hsiu Hsieh, Po-Han Su, Shao-Hsiang Chen, Yao-Wen Chang |
| 2024 | DAC | Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures. | Je-Wei Chuang, Zong-Han Wu, Bo-Ying Huang, Yao-Wen Chang |
| 2024 | DAC | Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards. | Wei-Che Tseng, Zong-Ying Cai, Yi-Ping Huang, Yu-Hsiang Lo, Yao-Wen Chang |
| 2024 | DAC | Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints. | Chien-Hao Tsou, Sheng-Yah Lin, Wei-Chen Hung, Yao-Wen Chang |
| 2024 | DATE | Electrostatics-Based Analytical Global Placement for Timing Optimization. | Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang |
| 2024 | ICCAD | Efficient High-Fidelity Two-Dimensional Warpage Modeling for Advanced Packaging Analysis. | Shao-Yu Lo, MaoZe Liu, Yao-Wen Chang |
| 2023 | DAC | PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. | Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, Jun Yu, Jianli Chen, Yao-Wen Chang |
| 2023 | DAC | Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology. | Wei-Hsu Chen, Yao-Wen Chang |
| 2023 | DAC | Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs. | Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang |
| 2023 | DAC | Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies. | Yan-Jen Chen, Yan-Syuan Chen, Wei-Che Tseng, Cheng-Yu Chiang, Yu-Hsiang Lo, Yao-Wen Chang |
| 2023 | DAC | Any-Angle Routing for Redistribution Layers in 2.5D IC Packages. | Min-Hsuan Chung, Je-Wei Chuang, Yao-Wen Chang |
| 2023 | DAC | A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints. | Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, Jianli Chen, Yao-Wen Chang |
| 2023 | DAC | Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. | Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang |
| 2023 | DAC | Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits. | Wei-Hsiang Tseng, Yao-Wen Chang |
| 2023 | ICCAD | A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs. | Yan-Lin Chen, Wei-Che Tseng, Wei-Yao Kao, Yao-Wen Chang |
| 2023 | ICCAD | Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. | Chung-Chia Lee, Yao-Wen Chang |
| 2022 | ASPDAC | Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. | Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang |
| 2022 | ASPDAC | High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. | Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang |
| 2022 | DAC | Flexible chip placement via reinforcement learning: late breaking results. | Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen |
| 2022 | DAC | Thermal-aware optical-electrical routing codesign for on-chip signal communications. | Yu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang |
| 2022 | DAC | Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. | Szu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang |
| 2022 | DAC | Subgraph matching based reference placement for PCB designs: late breaking results. | Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang |
| 2022 | DAC | A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits. | Wei-Hsiang Tseng, Yao-Wen Chang |
| 2022 | DAC | CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. | Huimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang |
| 2022 | DAC | High-performance placement for large-scale heterogeneous FPGAs with clock constraints. | Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang |
| 2022 | ICCAD | Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. | Yen-Ting Chen, Yao-Wen Chang |
| 2022 | ICCAD | Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. | Yang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin |
| 2022 | ICCAD | SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization. | Cheng-Yuan Wang, Yao-Wen Chang, Yuan-Hao Chang |
| 2021 | DAC | Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias. | Yu-Jie Cai, Yang Hsu, Yao-Wen Chang |
| 2021 | DAC | Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems. | Ming-Hung Chen, Yao-Wen Chang, Junjie Wang |
| 2021 | DAC | VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. | Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen |
| 2021 | DAC | A Bridge-based Compression Algorithm for Topological Quantum Circuits. | Chen-Hao Hsu, Wan-Hsuan Lin, Wei-Hsiang Tseng, Yao-Wen Chang |
| 2021 | DAC | Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection. | Bingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao-Wen Chang |
| 2021 | DATE | Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. | Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang |
| 2021 | ICCAD | On-chip Optical Routing with Waveguide Matching Constraints. | Fu-Yu Chuang, Yao-Wen Chang |
| 2021 | ICCAD | A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement. | Zih-Yao Lin, Yao-Wen Chang |
| 2021 | ICCAD | Time-Division Multiplexing Based System-Level FPGA Routing. | Wei-Kai Liu, Ming-Hung Chen, Chia-Ming Chang, Chen-Chia Chang, Yao-Wen Chang |
| 2021 | MOBICOM | Design and implementation of a generic 5G user plane function development framework. | Cheng-Ying Hsieh, Yao-Wen Chang, Chien Chen, Jyh-Cheng Chen |
| 2020 | ASPDAC | Unified Redistribution Layer Routing for 2.5D IC Packages. | Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang |
| 2020 | DAC | An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells | Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang |
| 2020 | DAC | Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. | Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang |
| 2020 | DAC | Latch Clustering for Timing-Power Co-Optimization. | Chau-Chin Huang, Gustavo E. Tllez, Gi-Joon Nam, Yao-Wen Chang |
| 2020 | DAC | Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. | Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang |
| 2020 | DAC | A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. | Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang |
| 2020 | DAC | Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. | Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang |
| 2020 | DAC | Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. | Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang |
| 2020 | ICCAD | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen |
| 2020 | ICCAD | Routability-Aware Pin Access Optimization for Monolithic 3D Designs. | Run-Yi Wang, Yao-Wen Chang |
| 2019 | ASPDAC | MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. | Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo |
| 2019 | DAC | A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. | Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang |
| 2019 | DAC | BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. | Fan-Keng Sun, Yao-Wen Chang |
| 2019 | ICCAD | Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. | Yu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang |
| 2019 | ICCAD | Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. | Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang |
| 2019 | ICCAD | Timing-Aware Fill Insertions with Design-Rule and Density Constraints. | Tingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang |
| 2019 | ICCAD | Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly. | Zhan-Ling Wang, Yao-Wen Chang |
| 2018 | DAC | WB-trees: a meshed tree representation for FinFET analog layout designs. | Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang |
| 2018 | DAC | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. | Run-Yi Wang, Chia-Cheng Pai, Junjie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang |
| 2018 | DAC | DSA-friendly detailed routing considering double patterning and DSA template assignments. | Hai-Juan Yu, Yao-Wen Chang |
| 2018 | DAC | Generalized augmented lagrangian and its applications to VLSI global placement. | Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang |
| 2018 | ICCAD | Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. | Shih-Chun Chen, Richard Sun, Yao-Wen Chang |
| 2018 | ICCAD | Novel proximal group ADMM for placement considering fogging and proximity effects. | Jianli Chen, Li Yang, Zheng Peng, Wenxing Zhu, Yao-Wen Chang |
| 2018 | ICCAD | Mixed-cell-height placement with complex minimum-implant-area constraints. | Jianli Chen, Peng Yang, Xingquan Li, Wenxing Zhu, Yao-Wen Chang |
| 2018 | ICCAD | A multithreaded initial detailed routing algorithm considering global routing guides. | Fan-Keng Sun, Hao Chen, Ching-Yu Chen, Chen-Hao Hsu, Yao-Wen Chang |
| 2018 | ICCAD | Mixed-cell-height placement considering drain-to-drain abutment. | Yu-Wei Tseng, Yao-Wen Chang |
| 2018 | ICCAD | Analytical solution of Poisson's equation and its application to VLSI global placement. | Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang |
| 2018 | ICCAD | Mixed-cell-height legalization considering technology and region constraints. | Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang |
| 2017 | ASPDAC | An effective legalization algorithm for mixed-cell-height standard cells. | Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo, Wenxing Zhu, Genghua Fan |
| 2017 | DAC | Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. | Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang |
| 2017 | DAC | Fogging Effect Aware Placement in Electron Beam Lithography. | Yu-Chen Huang, Yao-Wen Chang |
| 2017 | DAC | Graph-Based Logic Bit Slicing for Datapath-Aware Placement. | Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang |
| 2017 | DAC | Detailed Placement for Two-Dimensional Directed Self-Assembly Technology. | Zhi-Wen Lin, Yao-Wen Chang |
| 2017 | ICCAD | A novel damped-wave framework for macro placement. | Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen |
| 2017 | ICCAD | FPGA placement and routing. | Shih-Chun Chen, Yao-Wen Chang |
| 2017 | ICCAD | An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. | Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen |
| 2017 | ICCAD | Clock-aware placement for large-scale heterogeneous FPGAs. | Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo |
| 2017 | ICCAD | Redistribution layer routing for wafer-level integrated fan-out package-on-packages. | Ting-Chou Lin, Chia-Chih Chi, Yao-Wen Chang |
| 2017 | ICCAD | Mixed-cell-height detailed placement considering complex minimum-implant-area constraints. | Yen-Yi Wu, Yao-Wen Chang |
| 2017 | ICCAD | Blockage-aware terminal propagation for placement wirelength minimization. | Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen |
| 2016 | ASPDAC | Circular-contour-based obstacle-aware macro placement. | Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang |
| 2016 | ASPDAC | Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts. | Zhi-Wen Lin, Yao-Wen Chang |
| 2016 | ASPDAC | Recent research development and new challenges in analog layout synthesis. | Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung |
| 2016 | DAC | Timing-driven cell placement optimization for early slack histogram compression. | Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo |
| 2016 | DAC | Minimum-implant-area-aware detailed placement with spacing constraints. | Kai-Han Tseng, Yao-Wen Chang, Charles C. C. Liu |
| 2016 | DAC | QB-trees: towards an optimal topological representation and its applications to analog layout designs. | I-Peng Wu, Hung-Chih Ou, Yao-Wen Chang |
| 2016 | ICCAD | Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. | Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang |
| 2016 | ICCAD | VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology. | Yu-Hsuan Su, Yao-Wen Chang |
| 2016 | ICCAD | DSA-compliant routing for two-dimensional patterns using block copolymer lithography. | Yu-Hsuan Su, Yao-Wen Chang |
| 2015 | ASPDAC | Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. | Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang |
| 2015 | ASPDAC | Non-stitch triple patterning-aware routing based on conflict graph pre-coloring. | Po-Ya Hsu, Yao-Wen Chang |
| 2015 | ASPDAC | Detailed-Routing-Driven analytical standard-cell placement. | Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang |
| 2015 | DAC | EUV and e-beam manufacturability: challenges and solutions. | Yao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang |
| 2015 | DAC | Routing-architecture-aware analytical placement for heterogeneous FPGAs. | Sheng-Yen Chen, Yao-Wen Chang |
| 2015 | DAC | Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography. | Hung-Chih Ou, Kai-Han Tseng, Yao-Wen Chang |
| 2015 | DAC | Layout-dependent-effects-aware analytical analog placement. | Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang |
| 2015 | DAC | Nanowire-aware routing considering high cut mask complexity. | Yu-Hsuan Su, Yao-Wen Chang |
| 2015 | ICCAD | Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints. | Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang |
| 2015 | ICCAD | Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. | Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan |
| 2014 | DAC | Functional ECO Using Metal-Configurable Gate-Array Spare Cells. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2014 | DAC | Routability-Driven Blockage-Aware Macro Placement. | Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang |
| 2014 | DAC | A New Asynchronous Pipeline Template for Power and Performance Optimization. | Kuan-Hsien Ho, Yao-Wen Chang |
| 2014 | DAC | Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. | Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang |
| 2014 | DAC | Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. | Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang |
| 2014 | ICCAD | Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs. | Yu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang |
| 2014 | ICCAD | Fast lithographic mask optimization considering process variation. | Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee |
| 2014 | ICCD | Simultaneous EUV flare- and CMP-aware placement. | Chi-Yuan Liu, Yao-Wen Chang |
| 2014 | ISLPED | Buffered clock tree synthesis considering self-heating effects. | Chung-Wei Lin, Tzu-Hsuan Hsu, Xin-Wei Shih, Yao-Wen Chang |
| 2013 | ASPDAC | Layer minimization in escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng |
| 2013 | ASPDAC | Symmetrical buffered clock-tree synthesis with supply-voltage alignment. | Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao |
| 2013 | DAC | Double patterning lithography-aware analog placement. | Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang |
| 2013 | DAC | Stitch-aware routing for multiple e-beam lithography. | Shao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang |
| 2013 | DAC | Multiple chip planning for chip-interposer codesign. | Yuan-Kai Ho, Yao-Wen Chang |
| 2013 | DAC | Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. | Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao |
| 2013 | DAC | Routability-driven placement for hierarchical mixed-size circuit designs. | Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang |
| 2013 | DAC | An efficient and effective analytical placer for FPGAs. | Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang |
| 2013 | DAC | Simultaneous analog placement and routing with current flow and current density considerations. | Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang |
| 2012 | DAC | Timing ECO optimization using metal-configurable gate-array spare cells. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2012 | DAC | Structure-aware placement for datapath-intensive circuit designs. | Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang |
| 2012 | DAC | Simultaneous flare level and flare variation minimization with dummification in EUVL. | Shao-Yun Fang, Yao-Wen Chang |
| 2012 | DAC | A novel layout decomposition algorithm for triple patterning lithography. | Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen |
| 2012 | DAC | A chip-package-board co-design methodology. | Hsu-Chieh Lee, Yao-Wen Chang |
| 2012 | DAC | Obstacle-avoiding free-assignment routing for flip-chip designs. | Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen |
| 2012 | DAC | Non-uniform multilevel analog routing with matching constraints. | Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang |
| 2012 | DATE | Statistical thermal modeling and optimization considering leakage power variations. | Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang |
| 2011 | DAC | Simultaneous functional and timing ECO. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2011 | DAC | TSV-aware analytical placement for 3D IC designs. | Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov |
| 2011 | ICCAD | Timing ECO optimization via Bzier curve smoothing and fixability identification. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2011 | ICCAD | Heterogeneous B | Pang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang |
| 2011 | ICCAD | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. | Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu |
| 2011 | ICCAD | Escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang |
| 2011 | ICCAD | Routability-driven analytical placement for mixed-size circuit designs. | Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang |
| 2011 | ICCAD | A corner stitching compliant B | Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu |
| 2010 | ASPDAC | Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. | Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang |
| 2010 | ASPDAC | TRECO: dynamic technology remapping for timing engineering change orders. | Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang |
| 2010 | ASPDAC | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. | Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang |
| 2010 | DAC | Pulsed-latch aware placement for timing-integrity optimization. | Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang |
| 2010 | DAC | Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. | Cliff Chiung-Yu Lin, Yao-Wen Chang |
| 2010 | DAC | Fast timing-model independent buffered clock-tree synthesis. | Xin-Wei Shih, Yao-Wen Chang |
| 2010 | ICCAD | Native-conflict-aware wire perturbation for double patterning technology. | Szu-Yu Chen, Yao-Wen Chang |
| 2010 | ICCAD | Design-hierarchy aware mixed-size placement for routability optimization. | Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan |
| 2010 | ICCAD | Redundant-wires-aware ECO timing and mask cost optimization. | Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang |
| 2010 | ICCAD | Unified analytical global placement for large-scale mixed-size circuit designs. | Meng-Kai Hsu, Yao-Wen Chang |
| 2010 | ICCAD | Template-mask design methodology for double patterning technology. | Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif |
| 2010 | ICCAD | Recent research development in flip-chip routing. | Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee |
| 2010 | ICCAD | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. | Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang |
| 2010 | ICCD | Efficient provably good OPC modeling and its applications to interconnect optimization. | Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang |
| 2009 | ASPDAC | High-performance global routing with fast overflow reduction. | Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang |
| 2009 | DAC | Flip-chip routing with unified area-I/O pad assignments for package-board co-design. | Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang |
| 2009 | DAC | Spare-cell-aware multilevel analytical placement. | Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao |
| 2009 | DAC | ILP-based pin-count aware design methodology for microfluidic biochips. | Cliff Chiung-Yu Lin, Yao-Wen Chang |
| 2009 | DAC | Thermal-driven analog placement considering device matching. | Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang |
| 2009 | ICCAD | BIST design optimization for large-scale embedded memory cores. | Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng |
| 2009 | ICCAD | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. | Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang |
| 2009 | ICCAD | Simultaneous layout migration and decomposition for double patterning technology. | Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif |
| 2009 | ICCAD | An efficient pre-assignment routing algorithm for flip-chip designs. | Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng |
| 2008 | DAC | Predictive formulae for OPC with applications to lithography-friendly routing. | Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang |
| 2008 | DAC | Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs. | Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang |
| 2008 | DAC | A progressive-ILP based routing algorithm for cross-referencing biochips. | Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang |
| 2008 | ICCAD | Constraint graph-based macro placement for modern mixed-size circuit designs. | Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang |
| 2008 | ICCAD | Area-I/O flip-chip routing for chip-package co-design. | Jia-Wei Fang, Yao-Wen Chang |
| 2008 | ICCAD | Routing for chip-package-board co-design considering differential pairs. | Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang |
| 2008 | ICCAD | Multi-layer global routing considering via and wire capacities. | Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang |
| 2007 | ASPDAC | Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. | Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang |
| 2007 | DAC | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu |
| 2007 | DAC | An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. | Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang |
| 2007 | DAC | A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. | Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang |
| 2007 | ICCAD | Novel wire density driven full-chip routing for CMP variation control. | Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang |
| 2007 | ICCAD | ECO timing optimization using spare cells. | Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang |
| 2007 | ICCAD | An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
| 2007 | ICCAD | An efficient algorithm for statistical circuit optimization using Lagrangian relaxation. | I-Jye Lin, Yao-Wen Chang |
| 2007 | ICCAD | Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction. | Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang |
| 2007 | ICCAD | BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2007 | ISLPED | Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. | Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2006 | ASPDAC | A novel framework for multilevel full-chip gridless routing. | Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin |
| 2006 | ASPDAC | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. | Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen |
| 2006 | ASPDAC | Simultaneous block and I/O buffer floorplanning for flip-chip design. | Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang |
| 2006 | DAC | Novel full-chip gridless routing considering double-via insertion. | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han |
| 2006 | DAC | Placement of digital microfluidic biochips using the t-tree formulation. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2006 | ICCAD | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang |
| 2006 | ICCAD | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. | Zhe-Wei Jiang, Yao-Wen Chang |
| 2006 | ICCAD | Voltage island aware floorplanning for power and timing optimization. | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
| 2006 | ICCAD | Current path analysis for electrostatic discharge protection. | Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo |
| 2006 | ISCAS | Inductance extraction for general interconnect structures. | Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai |
| 2005 | ASPDAC | Multilevel full-chip gridless routing considering optical proximity correction. | Tai-Chen Chen, Yao-Wen Chang |
| 2005 | ASPDAC | Placement with symmetry constraints for analog layout design using TCG-S. | Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang |
| 2005 | ASPDAC | SoC test scheduling using the B-tree based floorplanning technique. | Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang |
| 2005 | DAC | Multilevel full-chip routing for the X-based architecture. | Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen |
| 2005 | DAC | An exact jumper insertion algorithm for antenna effect avoidance/fixing. | Bor-Yiing Su, Yao-Wen Chang |
| 2005 | ICCAD | IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
| 2005 | ICCAD | A routing algorithm for flip-chip design. | Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang |
| 2005 | ISCAS | RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2005 | ISLPED | Joint exploration of architectural and physical design spaces with thermal consideration. | Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang |
| 2005 | RTCSA | Reconfigurable Platform for Content Science Research. | Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen |
| 2004 | ASPDAC | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. | Yi-Hui Cheng, Yao-Wen Chang |
| 2004 | ASPDAC | Layout techniques for on-chip interconnect inductance reduction. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2004 | ASPDAC | Temporal floorplanning using 3D-subTCG. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen |
| 2004 | DAC | Efficient power/ground network analysis for power integrity-driven design methodology. | Su-Wei Wu, Yao-Wen Chang |
| 2004 | ICCAD | Temporal floorplanning using the T-tree formulation. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2004 | ICCD | Placement with Alignment and Performance Constraints Using the B*-Tree Representation. | Meng-Chen Wu, Yao-Wen Chang |
| 2004 | ISCAS | RLC effects on worst-case switching pattern for on-chip buses. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2003 | ASPDAC | Simultaneous floorplanning and buffer block planning. | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao |
| 2003 | ASPDAC | Noise-aware buffer planning for interconnect-driven floorplanning. | Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang |
| 2003 | ASPDAC | Graph matching-based algorithms for array-based FPGA segmentation design and routing. | Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang |
| 2003 | DAC | Multilevel floorplanning/placement for large-scale modules using B*-trees. | Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang |
| 2003 | ICCAD | A Fast Crosstalk- and Performance-Driven Multilevel Routing System. | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee |
| 2002 | DAC | TCG-S: orthogonal coupling of P | Jai-Ming Lin, Yao-Wen Chang |
| 2002 | DATE | Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. | Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang |
| 2002 | ICCAD | A novel framework for multilevel routing considering routability and performance. | Shih-Ping Lin, Yao-Wen Chang |
| 2001 | DAC | TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. | Jai-Ming Lin, Yao-Wen Chang |
| 2001 | ICCD | Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. | Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang |
| 2001 | ICCD | An Algorithm for Dynamically Reconfigurable FPGA Placement. | Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang |
| 2001 | ICCD | Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. | Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang |
| 2000 | DAC | An architecture-driven metric for simultaneous placement and global routing for FPGAs. | Yao-Wen Chang, Yu-Tsang Chang |
| 2000 | DAC | B*-Trees: a new representation for non-slicing floorplans. | Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu |
| 2000 | ICCD | Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. | Song-Ra Pan, Yao-Wen Chang |
| 2000 | ICCD | Rectilinear Block Placement Using B*-Trees. | Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang |
| 1999 | DAC | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang |
| 1999 | FPGA | Universal Switch Blocks for Three-Dimensional FPGA Design. | Guang-Ming Wu, Michael Shyu, Yao-Wen Chang |
| 1999 | ICCAD | A clustering- and probability-based approach for time-multiplexed FPGA partitioning. | Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 1999 | ICCD | Generic Universal Switch Blocks. | Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang |
| 1998 | ICCAD | Graph matching-based algorithms for FPGA segmentation design. | Yao-Wen Chang, Jai-Ming Lin, D. F. Wong |
| 1998 | ICCD | Timing-driven routing for symmetrical-array-based FPGAs. | Kai Zhu, Yao-Wen Chang, D. F. Wong |
| 1996 | DAC | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chung-Ping Chen, Yao-Wen Chang, D. F. Wong |
| 1996 | FPGA | Universal Switch-Module Design for Symmetric-Array-Based FPGAs. | Yao-Wen Chang, D. F. Wong, C. K. Wong |
| 1995 | ICCD | FPGA global routing based on a new congestion metric. | Yao-Wen Chang, D. F. Wong, C. K. Wong |
| 1995 | ICCD | Design and analysis of FPGA/FPIC switch modules. | Yao-Wen Chang, D. F. Wong, C. K. Wong |
| 1994 | ICCAD | A new global routing algorithm for FPGAs. | Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong |
| 1993 | ICCAD | Switch module design with application to two-dimensional segmentation design. | Kai Zhu, D. F. Wong, Yao-Wen Chang |